Intel STL2 User Manual

Page 3

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STL2 Server Board TPS

Table of Contents

Revision 1.0

iii

Table of Contents

1.

Introduction .....................................................................................................................1-1

1.1

Purpose ......................................................................................................................1-1

1.2

Audience ....................................................................................................................1-1

1.3

STL2 Server Board Feature Overview........................................................................1-1

1.4

STL2 Server Board Block Diagram.............................................................................1-2

2.

STL2 Server Board Architecture Overview ...................................................................2-5

2.1

Intel® Pentium® III Processor Subsystem ..................................................................2-5

1.1.1 Supported Processor Types....................................................................................2-5

1.1.2 Dual Processor Operation .......................................................................................2-6

1.1.3 PGA370 Socket.......................................................................................................2-6

1.1.4 Processor Bus Termination / Regulation / Power ....................................................2-6

1.1.5 Termination Package ..............................................................................................2-6

1.1.6 APIC Bus.................................................................................................................2-6

1.1.7 Boxed Processors ...................................................................................................2-6

1.2

ServerWorks ServerSet III LE Chipset........................................................................2-7

1.3

Memory.......................................................................................................................2-7

1.4

PCI I/O Subsystem .....................................................................................................2-8

1.4.1 64-bit / 66 MHz PCI Subsystem...............................................................................2-8

1.4.2 32-bit/33 MHz PCI Subsystem...............................................................................2-10

1.5

Chipset Support Components ..................................................................................2-15

1.5.1 Legacy I/O (Super I/O) National* PC97317VUL ....................................................2-15

1.5.2 BIOS Flash ............................................................................................................2-17

1.1.3 External Device Connectors ..................................................................................2-17

1.6

Interrupt Routing.......................................................................................................2-17

1.6.1 Default I/O APIC....................................................................................................2-17

1.6.2 Extended I/O APIC ................................................................................................2-17

1.6.3 PCI Ids...................................................................................................................2-20

1.6.4 Relationship between PCI IRQ and PCI Device ....................................................2-20

3.

Server Management ......................................................................................................3-23

3.1

Baseboard Management Controller..........................................................................3-23

3.2

Hardware Sensors....................................................................................................3-24

3.3

ACPI .........................................................................................................................3-27

3.4

AC Link Mode ...........................................................................................................3-28

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