Intel STL2 - Manual (Page 56)

Basic Input Output System (BIOS) STL2 Server Board TPS
4-48
mode operation, PHLASH (in non-interactive mode only) automatically updates only the main
system BIOS. PHLASH senses that STL2 is in recovery mode and automatically attempts to
update the system BIOS
Before powering up the system, the user must obtain a bootable diskette that contains a copy
of the BIOS recovery files. This is created by running the “crisdisk.bat” from the compressed
recovery file distributed with the BIOS.
Note: During recovery mode, video will not be initialized and many high-pitched beep tones will
be heard. The entire process takes two to four minutes. When the process is completed, the
tones will stop. The user may see a “Checksum error” on the first boot after updating the BIOS.
This is normal and should correct itself after the first boot.
If a failure occurs, it is most likely that of the system BIOS .ROM file is corrupt or missing.
After a successful update, power down the system and remove the jumper from pins 9-10.
Power up the system. Verify that the BIOS version number matches the version of the entire
BIOS used in the original attempt to update.
4.6 Error Messages and Error Codes
The system BIOS displays error messages on the video screen. Prior to video initialization,
beep codes inform the user of errors. POST error codes are logged in the event log. The BIOS
displays POST error codes on the video monitor.
Following are definitions of POST error codes, POST beep codes, and system error
messages.
4.6.1 POST Codes
The BIOS indicates the current testing phase during POST after the video adapter has been
successfully initialized by writing a 2-digit hex code to I/O location 80h. If a Port-80h card
(Postcard*) is installed, it displays this 2-digit code on a pair of hex display LEDs.
Table 4-23. Port-80h Code Definition
Code Meaning
CP Phoenix* check point (port-80) code
The table below contains the port-80 codes displayed during the boot process. A beep code is
a series of individual beeps on the PC speaker, each of equal length. The following table
describes the error conditions associated with each beep code and the corresponding POST
check point code as seen by a ‘port 80h’ card. For example, if an error occurs at checkpoint
22h, a beep code of 1-3-1-1 is generated. The “-“ means there is a pause between the
sequence that delimits the sequence.
Some POST codes occur prior to the video display being initialized. To assist in determining
the fault, a unique beep-code is derived from these checkpoints as follows: