Freescale Semiconductor MPC8260 - Manual (Page 1088)

ATM AAL2
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
32-26 Freescale Semiconductor
0x04 — — Reserved, should be cleared during initialization.
0x06 —
0x08 —
0x0A —
0x0C —
0x0E —
0x10 —
0x12 —
0x14 —
0x16 —
0x18 — CID Mapping
Table Base Points to the base address of the CID mapping table (see Figure 32-13 ).
If RCT[MAP] = 0, the pointer contains a dual-port RAM address and only the 16 lsb
(at 0x1A and 0x1B) are relevant. If MAP = 1, the pointer is a full 32-bit address in the
memory space.
0x1C 0–1 — Reserved, should be cleared during initialization.
2–7 PMT Performance monitoring table. Assigns one of the available 64 performance
monitoring tables to this VC. The table’s starting address is PMT_BASE+PMT*32.
8–15 TBNR Time
Out CNT The TBNR Time-Out CNT is a parameter that describes the amount of attempts the
transmitter tries to transmit a packet on a BD ring which is current marked as partially
filled, i.e. waiting for a receiver to finish reception of a packet.
This value will be used internally by the transmitter that is the destination for this
packet and decremeted by the CPM on each attempt. Upon reaching the value 1, the
transmitter will act as if the receiver is stuck in error condition and proceed to the next
BD in the BD ring. This parameter is valid in switch mode only and should be
programmed to a higher value than the ratio between the transmitter rate and the
lowest receiver rate in the BD ring. The 8 bit value is scaled by 4 (setting TBNR
Time-Out CNT =1 yields a value of 4 internally) so that the max number is 1K.
Clearing this field will disable this feature completely
0x1E 0–7 Max_CPS_S
DU_Deliver_
Length Indicates the maximum size CPS_SDU in bytes that is allowed to be transported on
this channel. This value is compared to the length of each CPS_SDU before it is
delivered, as specified in the ITU-T recommendation I.363.2.
8–13 — Reserved, should be cleared during initialization.
14 EM Receive error mask for AAL2 protocol-specific events. Note that buffer-not-ready, Rx
buffer and Rx frame events are not affected by this mask.
0 Disable AAL2 receive error events.
1 Enable AAL2 error events.
15 PM Enable performance monitoring
0 No performance monitoring for this VC.
1 Perform performance monitoring for this VC. Whenever a cell is received by this
VC, the associated performance monitoring table is updated.
1 Boldfaced entries must be initialized by the user.
Table 32-6. AAL2 Protocol-Specific RCT Field Descriptions
Offset Bits Name
1
Description