Freescale Semiconductor MPC8260 - Manual (Page 142)

G2 Core
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
2-24 Freescale Semiconductor
Program 00700 A program exception is caused by one of the following exception conditions, which
correspond to bit settings in SRR1 and arise during execution of an instruction:
• Illegal instruction—An illegal instruction program exception is generated when
execution of an instruction is attempted with an illegal opcode or illegal
combination of opcode and extended opcode fields (including PowerPC
instructions not implemented in the processor core), or when execution of an
optional instruction not provided in the processor core is attempted (these do not
include those optional instructions that are treated as no-ops).
• Privileged instruction—A privileged instruction type program exception is
generated when the execution of a privileged instruction is attempted and the
MSR register user privilege bit, MSR[PR], is set. In the processor core, this
exception is generated for mtspr or mfspr with an invalid SPR field if SPR[0] = 1
and MSR[PR] = 1. This may not be true for all processors that implement the
PowerPC architecture.
• Trap—A trap type program exception is generated when any of the conditions
specified in a trap instruction is met.
Floating-point
unavailable 00800 A floating-point unavailable exception is caused by an attempt to execute a
floating-point instruction (including floating-point load, store, and move instructions)
when the floating-point available bit is cleared (MSR[FP] = 0).
Decrementer 00900 The decrementer exception occurs when the most significant bit of the decrementer
(DEC) register transitions from 0 to 1. Must also be enabled with the MSR[EE] bit.
Reserved 00A00–00BFF —
System call 00C00 A system call exception occurs when a System Call (sc) instruction is executed.
Trace 00D00 A trace exception is taken when MSR[SE] = 1 or when the currently completing
instruction is a branch and MSR[BE] = 1.
Floating-point
assist 00E00 Not implemented.
Reserved 00E10–00FFF —
Instruction
translation
miss 01000 An instruction translation miss exception is caused when the effective address for an
instruction fetch cannot be translated by the ITLB.
Data load
translation
miss 01100 A data load translation miss exception is caused when the effective address for a
data load operation cannot be translated by the DTLB.
Data store
translation
miss 01200 A data store translation miss exception is caused when the effective address for a
data store operation cannot be translated by the DTLB, or when a DTLB hit occurs,
and the changed bit in the PTE must be set due to a data store operation.
Instruction
address
breakpoint 01300 An instruction address breakpoint exception occurs when the address (bits 0–29) in
the IABR matches the next instruction to complete in the completion unit, and the
IABR enable bit (bit 30) is set.
System
management
interrupt 01400 A system management interrupt is caused when MSR[EE] = 1 and the SMI input
signal is asserted.
Reserved 01500–02FFF —
Table 2-5. Exceptions and Conditions (continued)
Exception
Type
Vector Offset
(hex)
Causing Conditions