Freescale Semiconductor MPC8260 - Manual (Page 490)

Memory Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
11-72 Freescale Semiconductor
12 G1T1 General-purpose line 1 timing 1. Defines the state of GPL1 during phase 1–2.
0 The value of the GPL1 line at the rising edge of T1 will be 0
1 The value of the GPL1 line at the rising edge of T1 will be 1
See
Section 11.6.4.1.3, “General-Purpose Signals (GxTx, GOx) .”
13 G1T3 General-purpose line 1 timing 3. Defines the state of GPL1 during phase 3–4.
0 The value of the GPL1 line at the rising edge of T3 will be 0
1 The value of the GPL1 line at the rising edge of T3 will be 1
See
Section 11.6.4.1.3, “General-Purpose Signals (GxTx, GOx) .”
14 G2T1 General-purpose line 2 timing 1. Defines the state of GPL2 during phase 1–2.
0 The value of the GPL2 line at the rising edge of T1 will be 0
1 The value of the GPL2 line at the rising edge of T1 will be 1
See
Section 11.6.4.1.3, “General-Purpose Signals (GxTx, GOx) .”
15 G2T3 General-purpose line 2 timing 3. Defines the state of GPL2 during phase 3–4.
0 The value of the GPL2 line at the rising edge of T3 will be 0
1 The value of the GPL2 line at the rising edge of T3 will be 1
See
Section 11.6.4.1.3, “General-Purpose Signals (GxTx, GOx) .”
16 G3T1 General-purpose line 3 timing 1. Defines the state of GPL3 during phase 1–2.
0 The value of the GPL3 line at the rising edge of T1 will be 0
1 The value of the GPL3 line at the rising edge of T1 will be 1
See
Section 11.6.4.1.3, “General-Purpose Signals (GxTx, GOx) .”
17 G3T3 General-purpose line 3 timing 3. Defines the state of GPL3 during phase 3–4.
0 The value of the GPL3 line at the rising edge of T3 will be 0
1 The value of the GPL3 line at the rising edge of T3 will be 1
See
Section 11.6.4.1.3, “General-Purpose Signals (GxTx, GOx) .”
18 G4T/
DLT2 General-purpose line 4 timing 1/delay time 2. The function is determined by M x MR[GPL x 4DIS].
G4T1 If M x MR defines UPMWAITx/GPL_x4 as an output (GPL_x4), this bit functions as G4T1:
0 The value of the GPL4 line at the rising edge of T1 will be 0
1 The value of the GPL4 line at the rising edge of T1 will be 1
See
Section 11.6.4.1.3, “General-Purpose Signals (GxTx, GOx) .”
DLT3 If M x MR[GPL x 4DIS] = 1, UPMWAITx is chosen and this bit functions as DLT3.
0 In the current word, indicates that the data bus should be sampled at the rising edge of T1 (if a
read burst or a single read service is executed).
1 In the current word, indicates that the data bus should be sampled at the rising edge of T3 (if a
read burst or a single read service is executed).
For an example, see Section 11.6.4.3, “Data Valid and Data Sample Control .”
19 G4T3/
WAEN
General-purpose line 4 timing 3/wait enable. Function depends on the value of M x MR[GPL x 4DIS].
G4T3 If M x MR[GPL x 4DIS] = 0, G4T3 is selected.
0 The value of the GPL4 line at the rising edge of T3 will be 0
1 The value of the GPL4 line at the rising edge of T3 will be 1
WAEN If M x MR[GPL x 4DIS] = 1, WAEN is selected. See Section 11.6.4.5, “The Wait Mechanism .”
0 The UPMWAITx function is disabled.
1 A freeze in the external signal’s logical value occurs if the external wait signal is detected
asserted. This condition lasts until UPMWAITx is negated.
Table 11-36. RAM Word Bit Settings (continued)
Bit Name Description