Freescale Semiconductor MPC8260 - Manual (Page 678)

SDMA Channels and IDMA Emulation
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
19-34 Freescale Semiconductor
DCM[DINC] = 1 The destination memory address is incremented after every transfer.
IBASE=IBDPTR= 0x0030 The current BD pointer is set to the BD ring Base address (aligned 16 -bits[3–0]=0000).
DPR_BUF = 0x0800 Initiated to address aligned to 2048 (bits[10–0] = 000_0000_0000).
SS_MAX = 2016(0x07e0) Initiated to (internal buffer size - 32) equal to STS in this mode.
STS = 2016(0x07e0) Transfers from memory on PCI are 2016 bytes long on steady state of work.
DTS = 7*32 (0x00e0) Transfers to memory on 60x are 224 bytes long (7 60x bursts) for steady-state operations.
We have low arbitration priority on the bus (LP = 1) but once we get it we would like to use
it for more that one burst.
every BD[SDTB] = 1 Source memory is on the PCI (multiplexed with local) bus.
every BD[DDTB] = 0 Destination memory is on the 60x bus.
last BD[SDN] = 0 DONE is not asserted on the last transfer from memory on PCI.
last BD[DDN] = 0 DONE is not asserted on the last transfer to memory on the 60x bus.
last BD[L] = 1 IDMA1 is stopped after last BD complete untill START _ IDMA command is reissued.
last BD[I]] = 0 IDMA1 set BC interrupt to the core after last BD complete.
IDMR1=0x0f000000 IDMA1 Mask register is programmed to enable all interrupts.
SIMR_L=0x00000800 Interrupt controller is programmed to enable interrupts from IDMA1.
RCCR=0x00200000 IDMA1 configuration: Internal request priority is the lowest.
87FE=0x0100 IDMA1_BASE points to 0x0100 where the parameter table base address is located for
IDMA1.
CPCR=0x1e810009 IDMA_start command. IDMA1 page-00111 SBC-10100 op-1001 FLG=1. This write starts
the channel operation.
DMA operation:
START _ IDMA : Initialize all parameter RAM values, start transferring data immediately from the first BD. Data is read from
PCI bus in single burst of (32 aligment + 2016) bytes long, to fill internal buffer.The first write transfer to the 60x bus is
(32 aligment + 6 or 7 burst) bytes long. The rest 8 write transfers are 7 burst long each.
Steady state: Internal buffer is filled in large burst from PCI (STS long). Data is transferred to the 60x bus in 9 transfers
of 7 burst long (DTS) each. Addresses are incremented constantly. Operation continues until the last BD is completed
or
STOP _ IDMA command is issued. When the last valid BD is complete BC interrupt is set to the core, and IDMA1
channel is stopped, until START _ IDMA command is issued.
STOP _ IDMA : after all data in internal buffer is written to the 60x bus, BD is closed and SC interrupt is set. Channel is
stopped until START _ IDMA command is issued.
Table 19-17. Programming Example: Memory-to-Memory
(PCI-to-60x)—IDMA1 (continued)
Important Init Values Description