Freescale Semiconductor MPC8260 - Manual (Page 57)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor lv
Figures
Figure
Number
Title
Page
Number
25-4 Ethernet Address Recognition Flowchart ........................................................................... 25-11
25-5 Ethernet Mode Register (PSMR) ........................................................................................ 25-14
25-6 SCC Ethernet RxBD ........................................................................................................... 25-16
25-7 Ethernet Receiving using RxBDs ....................................................................................... 25-18
25-8 SCC Ethernet TxBD............................................................................................................ 25-19
25-9 SCC Ethernet Event Register (SCCE)/Mask Register (SCCM) ......................................... 25-20
25-10 Ethernet Interrupt Events Example ..................................................................................... 25-21
26-1 LocalTalk Frame Format....................................................................................................... 26-1
26-2 Connecting the PowerQUICC II to LocalTalk...................................................................... 26-3
27-1 SMC Block Diagram............................................................................................................. 27-1
27-2 SMC Mode Registers (SMCMR1/SMCMR2)...................................................................... 27-3
27-3 SMC Memory Structure........................................................................................................ 27-5
27-4 SMC Function Code Registers (RFCR/TFCR)..................................................................... 27-8
27-5 SMC UART Frame Format................................................................................................. 27-10
27-6 SMC UART RxBD ............................................................................................................. 27-14
27-7 RxBD Example ................................................................................................................... 27-16
27-8 SMC UART TxBD.............................................................................................................. 27-17
27-9 SMC UART Event Register (SMCE)/Mask Register (SMCM) ......................................... 27-18
27-10 SMC UART Interrupts Example......................................................................................... 27-19
27-11 Synchronization with SMSYNx.......................................................................................... 27-23
27-12 Synchronization with the TSA ............................................................................................ 27-24
27-13 SMC Transparent RxBD ..................................................................................................... 27-26
27-14 SMC Transparent Event Register (SMCE)/Mask Register (SMCM) ................................. 27-29
27-15 SMC Monitor Channel RxBD............................................................................................. 27-32
27-16 SMC Monitor Channel TxBD............................................................................................. 27-33
27-17 SMC C/I Channel RxBD..................................................................................................... 27-34
27-18 SMC C/I Channel TxBD..................................................................................................... 27-34
27-19 SMC GCI Event Register (SMCE)/Mask Register (SMCM) ............................................. 27-35
28-1 BD Structure for One MCC .................................................................................................. 28-3
28-2 TSTATE High Byte ............................................................................................................... 28-7
28-3 INTMSK Mask Bits .............................................................................................................. 28-8
28-4 Channel Mode Register (CHAMR) ...................................................................................... 28-8
28-5 Rx Internal State (RSTATE) High Byte .............................................................................. 28-10
28-6 Channel Mode Register (CHAMR)—Transparent Mode ................................................... 28-13
28-7 INTMSK Mask Bits ............................................................................................................ 28-15
28-8 Channel Mode Register (CHAMR)—CES Mode............................................................... 28-16
28-9 Extended Channel Mode Register (ECHAMR).................................................................. 28-22
28-10 SS7 Configuration Register (SS7_OPT) ............................................................................. 28-24
28-11 Mask1 Format ..................................................................................................................... 28-26
28-12 Mask2 Format ..................................................................................................................... 28-26
28-13 Super Channel Table Entry ................................................................................................. 28-29