Freescale Semiconductor MPC8260 - Manual (Page 21)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor xix
Contents
Paragraph
Number
Title
Page
Number
Chapter 13
IEEE 1149.1 Test Access Port
13.1 Overview........................................................................................................................ 13-1
13.2 TAP Controller............................................................................................................... 13-2
13.3 Boundary Scan Register................................................................................................. 13-3
13.4 Instruction Register........................................................................................................ 13-5
13.5 PowerQUICC II Restrictions ......................................................................................... 13-7
13.6 Nonscan Chain Operation .............................................................................................. 13-7
Chapter 14
Communications Processor Module Overview
14.1 Features .......................................................................................................................... 14-1
14.2 PowerQUICC II Serial Configurations.......................................................................... 14-3
14.3 Communications Processor (CP) ................................................................................... 14-4
14.3.1 CPM Performance Evaluation ................................................................................... 14-4
14.3.2 Features ...................................................................................................................... 14-4
14.3.3 CP Block Diagram ..................................................................................................... 14-5
14.3.4 G2 Core Interface....................................................................................................... 14-6
14.3.5 Peripheral Interface.................................................................................................... 14-7
14.3.6 Execution from RAM ................................................................................................ 14-8
14.3.7 RISC Controller Configuration Register (RCCR) ..................................................... 14-8
14.3.8 RISC Time-Stamp Control Register (RTSCR) ........................................................ 14-11
14.3.9 RISC Time-Stamp Register (RTSR) ........................................................................ 14-11
14.3.10 RISC Microcode Revision Number......................................................................... 14-12
14.4 Command Set............................................................................................................... 14-12
14.4.1 CP Command Register (CPCR)............................................................................... 14-13
14.4.1.1 CP Commands ..................................................................................................... 14-14
14.4.2 Command Register Example ................................................................................... 14-17
14.4.3 Command Execution Latency.................................................................................. 14-17
14.5 Dual-Port RAM............................................................................................................ 14-17
14.5.1 Buffer Descriptors (BDs)......................................................................................... 14-20
14.5.2 Parameter RAM ....................................................................................................... 14-20
14.6 RISC Timer Tables....................................................................................................... 14-22
14.6.1 RISC Timer Table Parameter RAM......................................................................... 14-22
14.6.2 RISC Timer Command Register (TM_CMD) ......................................................... 14-24
14.6.3 RISC Timer Table Entries........................................................................................ 14-24
14.6.4 RISC Timer Event Register (RTER)/Mask Register (RTMR) ................................ 14-24
14.6.5 set timer Command.................................................................................................. 14-25
14.6.6 RISC Timer Initialization Sequence ........................................................................ 14-25