Freescale Semiconductor MPC8260 - Manual (Page 527)

Secondary (L2) Cache Support
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 12-3
mode sacrifices some of the write performance of copy-back mode, but guarantees L2 cache coherency
with main memory.
Since write-through mode keeps memory coherent with the contents of the L2 cache, there is never any
need to perform an L2 copy-back. This removes the need for the L2 cache to maintain a dirty bit in the tag
RAM (all cache blocks are unmodified) and it also removes the need for bus arbitration signals.
The L2 cache is configured for write-through mode by pulling down it’s WT signal. There are no
configuration changes to the PowerQUICC II required in write-through mode. The PowerQUICC II can
also support additional bus masters (60x or PowerQUICC II type) in write-through mode.
Figure 12-2. shows a PowerQUICC II connected to a MPC2605 integrated L2 cache in write-through
mode.