NEC Network Controller uPD98502 - Manual (Page 147)

CHAPTER 2 V R 4120A
Preliminary User’s Manual S15543EJ1V0UM 147
2.5.4.6 NMI exception
(1) Cause
The Nonmaskable Interrupt (NMI) exception occurs when the NMI signal (internal) becomes active. This interrupt
is not maskable; it occurs regardless of the settings of the EXL, ERL, and IE bits in the Status register (for details,
see Section 2.8 CPU Core Interrupts).
(2) Processing
The CPU provides a special interrupt vector for this exception:
— BFC0_0000H (virtual) in 32-bit mode
— FFFF_FFFF_BFC0_0000H (virtual) in 64-bit mode
This vector is located within unmapped and uncached address space so that the cache and TLB need not be
initialized to process an NMI exception. The SR bit of the Status register is set to 1 to distinguish this exception
from a Cold Reset exception.
Unlike Cold Reset and Soft Reset, but like other exceptions, NMI is taken only at instruction boundaries. The
states of the caches and memory system are preserved by this exception.
When this exception occurs, the contents of all registers are preserved except for the following registers:
• The PC value at which an exception occurs is set to the ErrorEPC register.
• The TS bit of the Status register is cleared to 0.
• The ERL, SR, and BEV bits of the Status register are set to 1.
(3) Servicing
The NMI exception is serviced by:
• Preserving the current processor states for diagnostic tests
• Reinitializing the system in the same way as for a Cold Reset exception