3 registers, 1 register map, 2 tmmr (timer mode register) – NEC Network Controller uPD98502 User Manual

Page 425

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CHAPTER 9 TIMER

Preliminary User’s Manual S15543EJ1V0UM

425

9.3 Registers

9.3.1 Register map

Offset Address

Register Name

R/W

Access

Description

1000_00B0H

TMMR

R/W

W/H/B

Timer Mode Register

1000_00B4H

TM0CSR

R/W

W/H/B

Timer CH0 Count Set Register

1000_00B8H

TM1CSR

R/W

W/H/B

Timer CH1 Count Set Register

1000_00BCH

TM0CCR

R

W/H/B

Timer CH0 Current Count Register

1000_00C0H

TM1CCR

R

W/H/B

Timer CH1 Current Count Register

Remarks 1. In the “R/W” field,

“W” means “writeable”,

“R” means “readable”,

“RC” means “read-cleared”,

“- “ means “not accessible”.

2. All internal registers are 32-bit word-aligned registers.

3. The burst access to the internal register is prohibited.

If such burst access has been occurred, IRERR bit in NSR is set and NMI will assert to CPU.

4. Read access to the reserved area will set the CBERR bit in the NSR register and the dummy read

response data with the data-error bit set on SysCMD [0] is returned.

5. Write access to the reserved area will set the CBERR bit in the NSR register, and the write data is lost.

6. In the “Access” filed,

“W” means that word access is valid,

“H” means that half word access is valid,

“B” means that byte access is valid.

7. Write access to the read-only register cause no error, but the write data is lost.

8. The CPU can access all internal registers, but IBUS master device cannot access them.

9.3.2 TMMR (Timer Mode Register)

The Timer Mode Register “TMMR” is a read-write and 32-bit word-aligned register. TMMR is used to control the

timer. TMMR is initialized to 0 at reset and contains the following fields:

Bits

Field

R/W

Default

Description

31:9

Reserved

R/W

0

Hardwired to 0.

8

TM1EN

R/W

0

Timer CH1 enable:

1 = Enable, starts the timer CH1

(Automatically reloads the original timer value and starts if timer had expired)

0 = Disable, stops the timer

7:1

Reserved

R/W

0

Hardwired to 0.

0

TM0EN

R/W

0

Timer CH0 enable:

1 = Enable, starts the timer CH0

(Automatically reloads the original timer value and starts if timer had expired)

0 = Disable, stops the timer

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