NEC Network Controller uPD98502 - Manual (Page 269)

CHAPTER 4 ATM CELL PROCESSOR
Preliminary User’s Manual S15543EJ1V0UM 269
(2) Raw cell transmission
When host sends the non AAL-5 traffic packet which is not OAM F5 cell, host sets “AAL” bit in the packet
descriptor to a 0 and “PTI” field “0xx” which indicates user data. In this case, ATM Cell Processor doesn’t calculate or
add AAL-5 trailer.
If host sets “C10” bit in packet descriptor to a 1, ATM Cell Processor calculates and adds CRC-10 to each cell to
be transmitted.
Figure 4-29. Raw Cell with CRC-10
Header
5 bytes
Payload
46 bytes and 6bits
CRC-10
10 bits
Generation polynomial of CRC-10 is following:
G(x) = 1 + x + x 4 + x 5 + x 9 + x 10
4.8.2.4 Transmission indication
For each transmitted packet, ATM Cell Processor writes a send indication as a transmission completion status in
the mailbox. The mailbox used for transmission is mailbox 2 and 3. More specifically, ATM Cell Processor writes a
send indication once all the data in the packet has been read. The issuing of a send indication, therefore, does not
indicate that the sending of the packet to PMD has been completed.
Upon storing a send indication into the mailbox, ATM Cell Processor sets the corresponding MM bit of the A_GSR
register to a 1, and issues an interrupt if it is not masked.
The indication that ATM Cell Processor sends to the host during transmission is of the following format:
Figure 4-30. Send Indication Format
E VC Number A PACKET QUEUE POINTER
31 30 16 15 14 0
E (Error ID) Error ID indicates error condition.
0: Error
1: No error
VC Number VC Number used for this VC
A (for Active) If 0, indicates that the VC enters the idle state because the packet descriptor is invalid.
If 1, indicates that the VC is kept active because the next packet descriptor is valid.
Packet Queue Pointer Low-order 15 bits of the start address of the packet descriptor which is just transmitted.
4.8.2.5 Scheduling
ATM Cell Processor holds a scheduling table in which ATM Cell Processor sets the transmitting timings of all active
channels. Transmitting timing is recalculated each time ATM Cell Processor transmits a cell. Transmitting timing is
calculated using line rate and rate information which is set by V R 4120A prior to the Tx_Ready command. Rate
information is written in Tx VC table.