NEC Network Controller uPD98502 - Manual (Page 387)

CHAPTER 7 PCI CONTROLLER
Preliminary User’s Manual S15543EJ1V0UM 387
7.4.1.3 PCI Configuration Data Register (P_PCDR)
When bit31 in the PCAR register is set to ‘1’, access to PCDR register generates Configuration Cycle.
Read access to P_PCDR register generates Configuration Read Cycle on PCI bus. Write access to P_PCDR
register, also, generates Configuration Write Cycle on PCI bus.
7.4.1.4 IDSEL signals
As mentioned above, in address phase of Type0 transaction, the PCI Controller set one bit in AD [31:16] to ‘1’ and
all other bit to ‘0’. The PCI Controller decodes the device number field in P_PCAR register and selects the bit to be set
as below;
Table 7-1. Device Number Decode Table
Device Number AD [31:16]
00000 0000 0000 0000 0001
00001 0000 0000 0000 0010
00010 0000 0000 0000 0100
00011 0000 0000 0000 1000
00100 0000 0000 0001 0000
00101 0000 0000 0010 0000
00110 0000 0000 0100 0000
00111 0000 0000 1000 0000
01000 0000 0001 0000 0000
01001 0000 0010 0000 0000
01010 0000 0100 0000 0000
01011 0000 1000 0000 0000
01100 0001 0000 0000 0000
01101 0010 0000 0000 0000
01110 0100 0000 0000 0000
01111 1000 0000 0000 0000
1xxxx 0000 0000 0000 0000
The bits of AD [31:16] can be used as IDSEL signal. However, it maybe causes the violation for PCI electrical
specifications if AD [31:16] signal lines are connected to IDSEL ports of each PCI devices directly on boards.
Therefore, it will be desirable to insert resistors in the connections that these signal lines are connected to each PCI
device’s IDSEL port.
In this case, the delay may be caused before the time IDSEL input to PCI device becomes valid. The PCI
Controller always uses 2clock-address-continuous-stepping, taking into consideration the influence of this delay.