NEC Network Controller uPD98502 - Manual (Page 373)

CHAPTER 7 PCI CONTROLLER
Preliminary User’s Manual S15543EJ1V0UM 373
(2) Non posted write transaction
If IPWRD bit in P_BCNT register is ‘1’, the PCI Controller uses “Non Posted Write Transaction” rule for write
transactions from Internal bus-side to PCI-side. In this mode, burst transfers are disconnected at every single word.
The rule is as follows;
<1> An internal bus block
Note
connecting to the internal bus issues the write transaction to an external PCI target
device. The PCI Controller latches the first word of the burst data. A wait time is inserted until the latched
data is written to the PCI target device.
<2> The PCI Controller issues the write transaction to the external PCI target device.
<3> The PCI target device accepts the access.
<4> After the PCI transaction is completed, the PCI Controller issues “disconnect” to the internal bus block that
try to continue the write access as the burst transfer. The internal bus block should terminate the transaction
as soon as possible.
Note Internal bus feature is not described in this document. Internal bus has a similar feature to PCI bus. Then,
internal bus supports “disconnect” function.
Figure 7-3. Non Posted Write Transaction from Internal Bus to PCI
PCI
Controller
PCI
Target
Device
Internal
Bus Block
<1>
<4>
<2>
<3>
When the internal bus block wants to transfer more words, it should issue an additional write transaction.
If the PCI Controller receives target abort/master abort on PCI bus after it accepts non-posted-write from Internal
bus-side, it sets WRTAT/WRMAT bit of P_IGSR register and RTABT/RMABT bit of P_PGSR register, and issues
interrupts to an external PCI-Host device and the V R 4120A (if not masked). The PCI Controller will discard the data to
be written. Then, the PCI Controller can accept the new write transaction from Internal bus, again.