NEC Network Controller uPD98502 - Manual (Page 418)

CHAPTER 8 UART
418 Preliminary User’s Manual S15543EJ1V0UM
8.3.7 UARTIIR (UART Interrupt ID Register)
This register indicates priority levels for interrupts and existence of pending interrupt. From highest to lowest
priority, these interrupts are receive line status, receive data ready, character timeout, transmit holding register empty,
and modem status. The content of UARTIIR [3] bit is valid only in FIFO mode, and it is always 0 in 16550 mode.
UARTIIR [2] bit becomes 1 when UARTIIR [3] bit is set to 1.
Bits Field R/W Default Description
31:8 Reserved R 0 Hardwired to 0.
7:6 UFIFOEN R 00 UART FIFO is enable (read only):
Both bits set to 1 when the transmit/receive FIFO is enabled in the
UFIFOEN0 bit is set in the UARTFCR.
5:4 Reserved R 00 Hardwired to 0.
3:1 UIID R 000 Indicates the priority level of pending interrupt:
011 = 1st Priority: Receiver Line status
Overrun Error, Parity, Framing Error, or Break interrupt
010 = 2nd Priority: Received data available
Receiver Data Available or Trigger Level Reached
110 = 3rd Priority: Character timeout indication
No change in receiver FIFO during the last four character times and
FIFO is not empty.
001 = 4th Priority: Transmitter holding Register Empty
000 = 5th Priority: Modem Status (CTS_L, DSR_L or DCD_L.)
0 INTPENDL R 1 Pending interrupts
0 = UART Interrupt pending (read only)
1 = No UART interrupt pending