NEC Network Controller uPD98502 - Manual (Page 96)

CHAPTER 2 V R 4120A
96 Preliminary User’s Manual S15543EJ1V0UM
2.3.5.1 Exception conditions
When an exception condition occurs, the relevant instruction and all those that follow it in the pipeline are
cancelled. Accordingly, any stall conditions and any later exception conditions that may have referenced this
instruction are inhibited; there is no benefit in servicing stalls for a cancelled instruction.
When an exceptional conditions is detected for an instruction, the V
R
4120A will discard it and all following
instructions. When this instruction reaches the WB stage, the exception flag and various information items are written
to CP0 registers. The current PC is changed to the appropriate exception vector address and the exception bits of
earlier pipeline stages are cleared.
This implementation allows all preceding instructions to complete execution and prevents all subsequent
instructions from completing. Thus the value in the EPC is sufficient to restart execution. It also ensures that
exceptions are taken in the order of execution; an instruction taking an exception may itself be killed by an instruction
further down the pipeline that takes an exception in a later cycle.
Figure 2-20. Exception Detection
DC1 DC2 WB1
RF1 RF2 EX1 EX2 DC1 DC2 WB1
IF1 IF2 RF1 RF2 EX1 EX2 DC1 DC2 WB1
EX1 EX2
Exception vector
2
Exception
1
IF1 IF2 RF1 RF2 EX1 EX2 DC1 DC2 WB1 WB2
IF1 IF2 RF1 RF2 EX1 EX2 DC1 DC2 WB1 WB2
IF1 IF2 RF1 RF2 EX1 EX2 DC1 DC2 WB1 WB2
IF1 IF2 RF1 RF2 EX1 EX2 DC1 DC2 WB1 WB2
: Killed stage
: Interrupt