NEC Network Controller uPD98502 - Manual (Page 383)

CHAPTER 7 PCI CONTROLLER
Preliminary User’s Manual S15543EJ1V0UM 383
7.3 PCI Power Management Interface
The PCI Controller has the mechanism for power management compliant to PCI Power Management Interface
(PPMI) Rev.1.1 as a PCI-device. The PCI Controller does not control the power state of the chip, but issues signals of
power transition from the V
R
4120A to an external PCI-Host device, or from the PCI-Host device to the V
R
4120A. The
PCI-Host device and the V
R
4120A are responsible for the management of the power state.
The PCI Controller does not have the PCI bus control function for power management as a PCI-Host.
7.3.1 Power state
The PCI Controller supports D0, D1, D3hot and D3cold as PPMI states. Power Management Events (PME) would
be generated from D0, D1 and D3hot.
In PPMI Rev.1.1, D0 is defined as the maximum power state, D1 as the optional power management state, D3hot
as the power management state in which clock is suspended, D3cold as the power management state in which clock
is suspended and power is removed.
7.3.2 Power management event
The PCI Controller supports Power Management Events (PME) from D0, D1 and D3hot. PME shows the event that
issues the transition of the power state from device.
The PME is reported to an external PCI-Host device by asserting PME_B. The PCI Controller can assert PME_B.
When a ‘1’ is written to PMERQ bit in P_PPCR register, the PCI Controller asserts PME_B signal.
7.3.3 Power supply
The PCI Controller does not need the auxiliary power supply (Vaux), because the PCI Controller does not support
PME from D3cold.
The PCI Controller is designed on the assumption that there is no separated power supply, so that the transition to
D3cold state, in which the power is removed, means the power for all parts of the chip removed.
The reset signals may be separated for each bus, but in case of the wake-up from D3cold state, which is defined to
require the assertion of PCI-reset in PPMI Rev.1.1, all parts of the chip should be reset.