NEC Network Controller uPD98502 - Manual (Page 74)

CHAPTER 2 V R 4120A
74 Preliminary User’s Manual S15543EJ1V0UM
Table 2-11. Shift Instruction (Extended ISA)
Instruction Format and Description
Doubleword Shift Left
Logical
DSLL rd, rt, sa
The contents of register rt are shifted left by sa bits and zeros are inserted into the emptied lower bits.
The 64-bit result is stored into register rd.
Doubleword Shift Right
Logical
DSRL rd, rt, sa
The contents of register rt are shifted right by sa bits and zeros are inserted into the emptied higher
bits.
The 64-bit result is stored into register rd.
Doubleword Shift Right
Arithmetic
DSRA rd, rt, sa
The contents of register rt are shifted right by sa bits and the emptied higher bits are sign extended.
The 64-bit result is stored into register rd.
Doubleword Shift Left
Logical Variable
DSLLV rd, rt, rs
The contents of register rt are shifted left and zeros are inserted into the emptied lower bits. The lower
six bits of register rs specify the shift count.
The 64-bit result is stored into register rd.
Doubleword Shift Right
Logical Variable
DSRLV rd, rt, rs
The contents of register rt are shifted right and zeros are inserted into the emptied higher bits. The
lower six bits of register rs specify the shift count. The 64-bit result is stored into register rd.
Doubleword Shift Right
Arithmetic Variable
DSRAV rd, rt, rs
The contents of register rt are shifted right and the emptied higher bits are sign extended. The lower
six bits of register rs specify the shift count.
The 64-bit result is stored into register rd.
Doubleword Shift Left
Logical + 32
DSLL32 rd, rt, sa
The contents of register rt are shifted left by 32 + sa bits and zeros are inserted into the emptied lower
bits.
The 64-bit result is stored into register rd.
Doubleword Shift Right
Logical + 32
DSRL32 rd, rt, sa
The contents of register rt are shifted right by 32 + sa bits and zeros are inserted into the emptied
higher bits.
The 64-bit result is stored into register rd.
Doubleword Shift Right
Arithmetic + 32
DSRA32 rd, rt, sa
The contents of register rt are shifted right by 32 + sa bits and the emptied higher bits are sign
extended.
The 64-bit result is stored into register rd.
op rs rt funct rd sa