NEC Network Controller uPD98502 - Manual (Page 60)

CHAPTER 2 V R 4120A
60 Preliminary User’s Manual S15543EJ1V0UM
2.1.3 V R 4120A instruction set overview
For CPU instructions, there are only one type of instructions – 32-bit length instruction (MIPS III).
2.1.3.1 MIPS III instruction
All the CPU instructions are 32-bit length when executing MIPS III instructions, and they are classified into three
instruction formats as shown in Figure 2-3: immediate (I-type), jump (J-type), and register (R-type). The field of each
instruction format is described in Section 2.2 MIPS III Instruction Set Summary.
Figure 2-3. CPU Instruction Formats (32-bit Length Instruction)
0 16 15 21 20 26 25 31
op I-type (immediate)
J-type (jump)
R-type (register)
rs rt
op rs rt
op target
0 16 15 21 20 6 5 11 10 26 25 31
0 26 25 31
rd sa funct
immediate
The instruction set can be further divided into the following five groupings:
(a) Load and store instructions move data between memory and general-purpose registers. They are all
immediate (I-type) instructions, since the only addressing mode supported is base register plus 16-bit, signed
immediate offset.
(b) Computational instructions perform arithmetic, logical, shift, and multiply and divide operations on values in
registers. They include R-type (in which both the operands and the result are stored in registers) and I-type
(in which one operand is a 16-bit signed immediate value) formats.
(c) Jump and branch instructions change the control flow of a program. Jumps are always made to an absolute
address formed by combining a 26-bit target address with the high-order bits of the Program Counter (J-type
format) or register address (R-type format). The format of the branch instructions is I type. Branches have
16-bit offsets relative to the Program Counter. JAL instructions save their return address in register 31.
(d) Coprocessor 0 (System Control Coprocessor, CP0) instructions perform operations on CP0 registers to
control the memory-management and exception-handling facilities of the processor.
(e) Special instructions perform system calls and breakpoint operations, or cause a branch to the general
exception-handling vector based upon the result of a comparison. These instructions occur in both R-type
and I-type formats.
For the operation of each instruction, refer to Section 2.2 MIPS III Instruction Set Summary and APPENDIX A
MIPS III INSTRUCTION SET DETAILS.