NEC Network Controller uPD98502 - Manual (Page 150)

CHAPTER 2 V R 4120A
150 Preliminary User’s Manual S15543EJ1V0UM
(2) TLB invalid exception
(a) Cause
The TLB Invalid exception occurs when the TLB entry that matches with the virtual address to be referenced is
invalid (the V bit is set to 0). This exception is not maskable.
(b) Processing
The common exception vector is used for this exception. The TLBL or TLBS code in the ExcCode field of the
Cause register is set. If this exception has been caused by an instruction reference or load operation, TLBL is set.
If it has been caused by a store operation, TLBS is set.
When this exception occurs, the BadVAddr, Context, Xcontext, and EntryHi registers contain the virtual address
that failed address translation. The EntryHi register also contains the ASID from which the translation fault
occurred. The Random register normally stores a valid location in which to place the replacement TLB entry. The
contents of the EntryLo register are undefined.
The EPC register contains the address of the instruction that caused the exception. However, if this instruction is
in a branch delay slot, the EPC register contains the address of the preceding jump or branch instruction, and the
BD bit of the Cause register is set to 1.
(c) Servicing
Usually, the V bit of a TLB entry is cleared in the following cases:
— When a virtual address does not exist
— When the virtual address exists, but is not in main memory (a page fault)
— When a trap is required on any reference to the page (for example, to maintain a reference bit)
After servicing the cause of a TLB Invalid exception, the TLB entry is located with a TLBP (TLB Probe) instruction,
and replaced by an entry with its V bit set to 1.