NEC Network Controller uPD98502 - Manual (Page 171)

CHAPTER 2 V R 4120A
Preliminary User’s Manual S15543EJ1V0UM 171
2.7.2.3 Accessing the caches
Figure 2-69 shows the virtual address (VA) index into the caches. The number of virtual address bits used to index
the instruction and data caches depends on the cache size.
(1) Data cache addressing
Using VA (12:4). The most-significant bit is VA12 because the cache size is 8 Kbytes.
The least-significant bit is VA4 because the line size is 4 words (16 bytes).
(2) Instruction cache addressing
Using VA (13:4). The most-significant bit is VA13 because the cache size is 16 Kbytes.
The least-significant bit is VA4 because the line size is 4 words (16 bytes).
Figure 2-69. Cache Data and Tag Organization
Tags
Tag line
VA (12:4)
for data cache (8 Kbytes)
VA (13:4)
for instruction cache (16 Kbytes)
V Tag W P
Data
Data line
Data
64
2.7.3 Cache operations
As described earlier, caches provide temporary data storage, and they make the speedup of memory accesses
transparent to the user. In general, the CPU core accesses cache-resident instructions or data through the following
procedure:
1. The CPU core, through the on-chip cache controller, attempts to access the next instruction or data in the
appropriate cache.
2. The cache controller checks to see if this instruction or data is present in the cache.
— If the instruction/data is present, the CPU core retrieves it. This is called a cache hit.
— If the instruction/data is not present in the cache, the cache controller must retrieve it from memory.
This is called a cache miss.
3. The CPU core retrieves the instruction/data from the cache and operation continues.
It is possible for the same data to be in two places simultaneously: main memory and cache. This data is kept
consistent through the use of a write-back methodology; that is, modified data is not written back to memory until the
cache line is to be replaced.
Instruction and data cache line replacement operations are described in the following sections.