Cirrus Logic EP93xx - Manual (Page 124)

4-6 DS785UM1
Copyright 2007 Cirrus Logic
Boot ROM
EP93xx User’s Guide
4
4
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4.2.1 UART Boot
Make sure that the boot configuration pins (see Table 5-1 on page 5-2 ) are configured for
internal boot mode. EEDAT and BOOT0 should be pulled high and BOOT1 should be pulled
low as shown in
Table 5-2 on page 5-3 . UART 1 is configured at 9600 bps, 8-bits, No Parity,
No flow control. The code performs:
1. A single “<“ is output by UART 1
2. The ASCII “CRUS” or “SURC” value in the HeaderID is read
3. 2048 characters are received by UART 1 and copied to the Ethernet buffer at address
0x8001_4000
4. The ARM Core will jump to 0x8001_4000. The ARM Core will be in SVC mode when the
jump occurs.
4.2.2 SPI Boot
To boot from an SPI Serial Flash device, make sure that the boot configuration pins (see
Table 5-1 on page 5-2 ) are configured for internal boot mode. EEDAT should be pulled high
and LBOOT1 and LBOOT0 should be pulled low as shown in Table 5-2 on page 5-3 .
To boot from the SPI ROM, place the ASCII “CRUS” or “SURC” value in the HeaderID at the
first location in the ROM. The code will be copied from the SPI ROM to the Ethernet buffer at
address 0x8001_4000 with a length of 2048 bytes. Code execution will start at 0x8001_4000
(MAC base + 0x4000). The ARM Core will be in SVC mode. At this point the user can use the
code in the MAC buffer to load the rest of the image from the SPI ROM.
4.2.3 FLASH Boot
To enable FLASH boot, make sure that the boot configuration pins (see Table 5-1 on page 5-
2 ) are configured for normal boot mode, as shown in Table 4-1 . Also make sure that the
FLASH word size is correct as shown in Table 4-1 .
To boot from FLASH, put the ASCII “CRUS” or “SURC” value in the HeaderID at one of the
following locations (this location will be referred to as FLASH base + 0x0):
0x1000_0000
0x2000_0000
0x3000_0000
0x6000_0000
0x7000_0000
Code execution will start at address FLASH base + 0x4. The ARM Core will be in SVC mode.
Alternatively, to boot from FLASH, put the ASCII “CRUS” or “SURC” value in the HeaderID at
one of the following locations (this location will be referred to as FLASH base +0x1000):
0x1000_1000
0x2000_1000