Cirrus Logic EP93xx - Manual (Page 779)

DS785UM1 27-9
Copyright 2007 Cirrus Logic
IDE Interface
EP93xx User’s Guide
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27
27.2.7.3.3 Ultra DMA Read from IDE Controller
Follow the wait-state number listed in the wait-state table in Table 27-3 and Table 27-4 .
However, the DMA request will not assert unless there are 4 words present in the read FIFO
or the transfer is non-quad aligned and has the last remaining bits of data, so quad-word
bursts are permissible if the total Ultra DMA transfer size is quad-word aligned.
27.2.7.3.4 Ultra DMA Write to IDE Controller
Although the DMA request line has a non-insignificant DMAIDE latency, the DMA write FIFO
is of sufficient size to absorb any overage incurred during the DMA request latency period.
The DMA controller can be run without wait-states. Quad-word bursts are permissible if the
Ultra DMA transfer size is quad-word aligned.
27.2.8 IDE Package Dependency
The block uses the following external pins:
IDECS0n, IDECS1n, IDEDA, DIORn, DIOWn, DMACKn, DD, IORDY, INT[3], EGPIO[2],
and EGPIO[15].
27.2.8.1 System Configuration Constraints
The following system configuration modes force the disabling of the IDE controller:
- GPIOEonIDE
- GPIOFonIDE
- GPIOGonIDE
- GPIOHonIDE
27.2.8.2 Bus Bandwidth Requirements
The block does not have any hard bandwidth constraints because it can throttle performance
to the available bandwidth without data corruption. The maximum free bandwidth that the
block will consume is limited by the IDE mode the device is in. Maximum theoretical
bandwidths are listed in
Table 27-5 .
Table 27-5. Maximum Theoretical Bandwidths for Various Operating Modes
Mode MAX IDE Device Bandwidth
PIO Mode 0 3.33 MBps
PIO Mode 1 5.22 MBps
PIO Mode 2 8.33 MBps
PIO Mode 3 11.11 MBps
PIO Mode 4 16.67 MBps
MDMA Mode 0 4.17 MBps
MDMA Mode 1 13.33 MBps
MDMA Mode 2 16.67 MBps