Cirrus Logic EP93xx - Manual (Page 40)

2-2 DS785UM1
Copyright 2007 Cirrus Logic
ARM920T Core and Advanced High-Speed Bus (AHB)
EP93xx User’s Guide
2
2
2
2.2.2 Block Diagram
Figure 2-1. ARM920T Block Diagram
2.2.3 Operations
The ARM920T core follows a Harvard architecture and consists of an ARM9TDMI core,
MMU, instruction and data cache. The core supports both the 32-bit ARM and 16-bit Thumb
instruction sets.
The internal bus structure (AMBA) includes both a high speed and low speed bus. The high
speed bus AHB (Advanced High-performance Bus) contains a high speed internal bus clock
to synchronize co-processor, MMU, cache, DMA controller, and memory modules. AMBA
includes a AHB/APB bridge to the lower speed APB (Advanced Peripheral Bus). The APB
bus connects to lower speed peripheral devices such as UARTs and GPIOs.
The MMU provides memory address translation for all memory and peripherals designed to
remap memory devices and peripheral address locations. Sections, large, small and tiny
pages are programmable to map memory in 1 Mbyte, 64 kbyte, 4 kbyte, 1 kbyte size blocks.
To increase system performance, a 64-entry translation look-aside buffer will cache 64
address locations before a TLB miss occurs.
External
Co-Proc
Interface
Instruction
cache
Instruction
MMU
Data cache Data MMU
Write Back
PA TAG
RAM
AMBA
Bus
Int.
R13
R13
ARM9TDMI
Processor core
(Integral
EmbeddedICE)
CP15
Write
Buffer
JTAG
APB