Table 5-3. clock speeds and sources -8 – Cirrus Logic EP93xx User Manual

Page 134

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5-8

DS785UM1

Copyright 2007 Cirrus Logic

System Controller
EP93xx User’s Guide

5

5

5

Even though FCLK is the usual CPU clock, HCLK can optionally be used instead. Processor
clocking modes are:

Async mode

Sync mode

Fast Bus mode

Both Async mode and Sync mode use FCLK. FCLK can be faster than HCLK, which would
yield higher performance. Async mode and Sync mode have different clock skew
requirements between FCLK and HCLK, and therefor have different throughput penalties due
to clock synchronization. Fast Bus mode bypasses FCLK, and the CPU runs from HCLK. In
this mode, the ARM Core potentially has lower performance than with the other two modes.
When the ARM Core starts up, it defaults to Fast Bus mode. (The selection of clocking
modes is determined by the iA and nF bits in ARM co-processor 15 register 1.)

5.1.5.2.2 Peripheral Clock Generation

The MCLK, VCLK, and MIR_CLK generators are three identical blocks. Each block contains
a pre-divider of 2, 2.5 and 3 followed by a 7-bit programmer divider. The audio clock SCLK
and LRCLK are further divided down from MCLK. The registers,

“MIRClkDiv” on page 5-30

,

“VidClkDiv” on page 5-29

, and

“I2SClkDiv” on page 5-31

, show the details.

USB uses a 48 MHz clock generated by PLL2. USBDIV, in register

“ClkSet2” on page 5-20

, is

used to divide the frequency down from the PLL2 output.

The Key Matrix and Touchscreen Controller clocks are generated from an external 14.7 MHz
oscillator. A chain of dividers generates divide-by-2, 4, 8, 16, 32, 64 versions of external
oscillator clock. Programmable bits in the

“KeyTchClkDiv” on page 5-32

select either a divide-

by-4 or a divide-by-16 version of the external oscillator clock for each of the Key Matrix clock
and Touchscreen controller.

Table 5-3

describes the speeds and sources for the various clocks.

Table 5-3. Clock Speeds and Sources

Block

Clocks Used

Clock Source

SSP

7.3728 MHz

Divided by 2 from 14.7456 MHz external oscillator

UART1
UART2
UART3

14.7456 MHz

7.3728 MHz

Both are derived from 14.7456 MHz external oscillator

PWM

14.7456 MHz

From the 14.7456MHz external oscillator

AAC

2.9491 MHz

Divided-by-5 from the 14.7456MHz external oscillator

Timers

508.4689 KHz

1.9939 KHz

983 KHz

All divided by the 14.7456 MHz external oscillator

Watchdog

256 Hz

Tap from the 32 KHz RTC clock

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