Standby and halt, Teoi, Rsvd: there are no readable bits in this register – Cirrus Logic EP93xx User Manual
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DS785UM1
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Copyright 2007 Cirrus Logic
System Controller
EP93xx User’s Guide
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5
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Standby and Halt
Address:
Standby - 0x8093_000C - Read Only
Halt - 0x8093_0008 - Read Only
Definition:
The Standby and Halt registers allow entry into the power saving modes. A
read to the Halt location will initiate a request for the system to enter Halt
mode, if the SHena bit is set in the DeviceCfg register in Syscon. Likewise a
read to Standby will request entry into Standby only when the SHena bit is set.
Note: When a read is performed to the Standby location, it must be immediately followed by 5
NOP instructions. This is needed to flush the instruction pipeline in the ARM920T core.
Writes to these locations have no effect.
Bit Descriptions:
RSVD:
There are no readable bits in this register.
TEOI
Address:
0x8093_0018 - Write
Definition:
Writing to the TEOI location will clear the periodic Watchdog expired interrupt
(WEINT) and the 64 Hz TICK interrupt (TINT). Any data written to the register
triggers the clearing.
Bit Descriptions:
RSVD:
There are no readable bits in this register.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD