Cirrus Logic EP93xx - Manual (Page 710)

22-22 DS785UM1
Copyright 2007 Cirrus Logic
AC’97 Controller
EP93xx User’s Guide
2
2
2
2
22
AC97Reset
Address:
0x8088_00A0 - Read/Write
Definition:
Controller Reset Register. The AC’97 Controller RESET register is a
read/write register that controls various functions within the AC’97 Controller
of the RESET port. All the register bits are cleared to “0” when reset.
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
EFORCER: Enable for the Forced RESET bit.
1 - FORCEDRESET become active
0 - FORCEDRESET has no effect.
FORCEDRESET: If the EFORCER bit is set to “1”, the RESET port will follow
whatever value is written to this bit. If this mechanism is
used to control the RESET port, it is up to software to
ensure that the signal is high long enough to meet the
specification of the external device.
This bit has priority over the TIMEDRESET bit.
TIMEDRESET: If this bit is set to “1”, the RESET port is forced to “0” for
five pulses of the 2.9491 MHz clock
(0.339 µs x 5 = 1.695 µs maximum reset pulse and
1.356 µs minimum reset pulse using this 2.9491 MHz
clock). After which this bit is zeroed.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD EFORCER FORCED
RESET
TIMED
RESET