Blksrcstrt – Cirrus Logic EP93xx User Manual
Page 288
8-24
DS785UM1
Copyright 2007 Cirrus Logic
Graphics Accelerator
EP93xx User’s Guide
8
8
8
Default:
0x0000_0000
Mask:
0x001F_001F
Definition:
Destination Pixel Start/End register
Bit Descriptions:
RSVD:
Reserved - Unknown during read
EPEL:
Destination Pixel Location - Read/Write
For the ending pixel (at the ending X-Y coordinate of the
1st scan line) of the destination image for a block copy, the
value in this field specifies where the beginning bit of the
ending pixel is located in a 32-bit word. For example, if the
beginning bit of an 8-bit pixel is located at bit 24 of a 32-bit
word, EPEL = 0x18.
The EPEL field and the ADR field in the
register together define the destination ending pixel’s
address in the SDRAM frame buffer. Granularity must be a
multiple of the pixel size in all video display modes. For
example,.acceptable values in 8 bpp mode are 0x00,
0x08, 0x10, and 0x18.
SPEL:
Source Pixel Location - Read/Write
For the starting pixel (at the starting X-Y coordinate of the
1st scan line) of the destination image for a block copy, the
value in this field specifies where the beginning bit of the
pixel is located in a 32-bit word. For example, if the
beginning bit of a 16-bit pixel is located at bit 16 of a 32-bit
word, PEL = 0x10.
The SPEL field and the ADR field in the
register together define the destination starting pixel’s
address in the SDRAM frame buffer. Granularity must be a
multiple of the pixel size in all video display modes. For
example,.acceptable values in 8 bpp mode are 0x00,
0x08, 0x10, and 0x18.
BLKSRCSTRT
Address:
0x8004_0008 - Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ADR
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADR
NA