Figure 7-1. raster engine block diagram -8 – Cirrus Logic EP93xx User Manual
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DS785UM1
Copyright 2007 Cirrus Logic
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
7
7
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Figure 7-1. Raster Engine Block Diagram
7.4.1 VILOSATI (Video Image Line Output Scanner and Transfer
Interface)
The Raster Engine’s video image line output scanner and transfer interface connects to a
either a dedicated DMA port on the SDRAM controller or to AHB access to the SDRAM
controller and reads the video image from SDRAM to the video FIFO. VILOSATI keeps track
of image location, width, and depth for both progressive and dual scanned images. It
responds to controls from the FIFO for more video information. During single scan operation,
when the FIFO level falls below a programmable fill level (FIFOLevel defaults to a value of 16
words), the FULL signal is inactive and VILOSATI attempts to initiate an unspecified length
incrementing burst of at least 16 words. The VILOSATI will initiate incrementing unspecified
length bursts until the FIFO is full. When the FIFO signals that it has emptied below the
FIFOLevel again, the image reading process from the frame buffer continues.
Note: FIFOLevel values of greater than 16 words are not recommended due to the possibility of
FIFO underflow.
For dual scan operation, the FIFO is split into two halves, where each halve operates with a
separate FULL indicator. In dual scan mode, selected by writing DSCAN = ‘1’ to the
register, the FULL and DS_FULL indicators trigger when either has room for a
burst of 8 words (the LSB of FIFOLevel is ignored). For dual and single scan displays,
information for the upper left corner of the display begins at the word address stored in the
DAT(31:0)
PELEN
P[17:0]
FIFO
N_WR
N_RD
FULL
HFULL
N_CLR
SYNCEN
N/V/CSYNC
HSYNC/LP
BLANK
BRIGHT
Compare
and
register
logic
64
24
S/PCLK
PCLKEN
ADR(31:0)
8
24
24
3
CREQ
CGNT
2
24
To
DAC
24
CCIREN
Video Stream
Signature Analyzer
HDAT(31:0)
HADR(31:0)
Two
32x32
Dual
Port
RAMs
Video
Image
Line
Output
Scanner
And
Transfer
Interface
IN
ADR
CTR
OUT
ADR
CTR
Control
Logic
Cursor
Address
CNTRs
AMBA
Cursor
Bus
Master
Cursor
State
Machs
Cursor
Line
Buffer
Pixel
MUX
Color
MUX
24
Blink
Logic
256x24
SRAM
Look
Up
Table
Gray
Scale
Gen
YCrCb
Encoder
Pixel
Shifting
Logic
Horizontal
and
Vertical
Counters
Cursor
Output
CNTRs