Vblankstrtstop – Cirrus Logic EP93xx User Manual
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DS785UM1
Copyright 2007 Cirrus Logic
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
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VBlankStrtStop
Address: 0x8003_0228
Default: 0x0000_0000
Definition: Vertical BLANK signal Start/Stop register
Bit Descriptions:
RSVD:
Reserved - Unknown during read
STOP:
Stop - Read/Write
The STOP value is the value of the Vertical down counter
at which the VBLANKn signal becomes inactive (stops).
This is used to generate the BLANKn signal that is used
by external devices and indicates the end of the active
video portion for the Vertical frame. Please refer to video
signalling timing diagrams in
VBLANKn is an internal block signal. The NBLANK output
is a logical AND of NVBLANK and HBLANKn.
STRT
:
Start - Read/Write
The STRT value is the value of the Vertical down counter
at which the VBLANKn signal becomes active (starts).
This is used to generate the BLANKn signal that is used
by external devices and indicates the start of the active
video portion for the Vertical frame. Please refer to video
signalling timing diagrams in
VBLANKn is an internal block signal. The NBLANK output
is a logical AND of NVBLANK and HBLANKn.
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RSVD
STOP
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0
RSVD
STRT