Avago Technologies LSI8751D - Manual (Page 103)

4-11
Table 4.5 describes the Address and Data Signals group.
Table 4.5 Address and Data Signals
Name Pin No.
Typ
e Description
AD[31:0] LSI53C875
LSI53C875J:
150, 151, 153, 154,
156, 157, 159, 160,
3, 5, 6, 7, 9, 11, 12,
13, 28, 29, 30, 32,
34, 35, 36, 38, 40,
41, 43, 44, 46, 47,
49, 50
LSI53C875N:
194, 195, 197, 198,
200, 201, 203, 204,
9, 11, 12, 13, 15,
17, 18, 19, 35, 36,
37, 39, 41, 42, 43,
45, 48, 58, 60, 61,
63, 64, 66, 67
LSI53C875JB:
B5, C5, A4, B4, A3,
C4, D4, A2, C2, E5,
C1, D3, E4, E3, E2,
E1, H5, J1, J2, H6,
K2, J4, L1, L2, M1,
N1, M3, L3, N3, L4,
K5, N4
T/S Physical longword Address and Data are multiplexed
on the same PCI pins. During the first clock of a
transaction, AD[31:0] contain a physical address.
During subsequent clocks, AD[31:0] contain data. A
bus transaction consists of an address phase, followed
by one or more data phases. PCI supports both read
and write bursts. AD[7:0] define the least significant
byte, and AD[31:24] define the most significant byte.
C_BE[3:0]/ LSI53C875
LSI53C875J:
1, 15, 26, 39
LSI53C875N:
6, 21, 32, 46
LSI53C875JB:
A1,F3, H3, K4
T/S Bus Command and Byte Enables are multiplexed on
the same PCI pins. During the address phase of a
transaction, C_BE[3:0]/ define the bus command.
During the data phase, C_BE[3:0]/ are used as byte
enables. The byte enables determine which byte lanes
carry meaningful data. C_BE[0]/ applies to byte 0, and
C_BE[3]/ to byte 3.