Table 4.7 arbitration signals, Arbitration signals – Avago Technologies LSI8751D User Manual
Page 105
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describes the Arbitration Signals group.
IRDY/
17/23/F1
S/T/S
Initiator Ready indicates the initiating agent’s (bus master’s)
ability to complete the current data phase of the transaction.
IRDY/ is used with TRDY/. A data phase is completed on any
clock when both IRDY/ and TRDY/ are sampled asserted. During
a write, IRDY/ indicates that valid data is present on AD[31:0].
During a read, it indicates that the master is prepared to accept
data. Wait cycles are inserted until both IRDY/ and TRDY/ are
asserted together.
STOP/
22/28/G4
S/T/S
Stop indicates that the selected target is requesting the master
to stop the current transaction.
DEVSEL/
20/26/G2
S/T/S
Device Select indicates that the driving device has decoded its
address as the target of the current access. As an input, it
indicates to a master whether any device on the bus has been
selected.
IDSEL
2/7/B1
I
Initialization Device Select is used as a chip select in place of
the upper 24 address lines during configuration read and write
transactions.
Table 4.6
Interface Control Signals (Cont.)
Name
Pin No.
LSI53C875,
LSI53C875J,
LSI53C875N,
LSI53C875JB
Type
Description
Table 4.7
Arbitration Signals
Name
Pin No.
LSI53C875,
LSI53C875J,
LSI53C875N,
LSI53C875JB
Typ
e
Description
REQ/
148/191/E6
O
Request indicates to the system arbiter that this agent desires use of
the PCI bus. This is a point-to-point signal. Every master has its own
REQ/ signal.
GNT/
147/190/D6
I
Grant indicates to the agent that access to the PCI bus has been
granted. This is a point-to-point signal. Every master has its own
GNT/ signal.