2 3.3 v/5 v pci interface, 3 additional access to general purpose pins, 3 v/5 v pci interface – Avago Technologies LSI8751D User Manual
Page 33: Additional access to general purpose pins
PCI Cache Mode
2-9
2.5.2 3.3 V/5 V PCI Interface
The LSI53C875 can attach directly to a 3.3 V or a 5 V PCI interface, due
to separate V
DD
pins for the PCI bus drivers. This allows the devices to
be used on the universal board recommended by the PCI Special
Interest Group.
2.5.3 Additional Access to General Purpose Pins
The LSI53C875 can access the GPIO0 and GPIO1 general purpose pins
through register bits in the PCI configuration space, instead of using the
General Purpose Pin Control (GPCNTL)
register in the operating register
space to control these pins. In the LSI Logic SDMS software, the
configuration bits control pins as the clock and data lines, respectively.
To access the GPIO[1:0] pins through the configuration space, connect
a 4.7 k
Ω
resistor between the MAD[7] pin and V
SS
. MAD[7] contains an
internal pull-up that is sensed shortly after chip reset. If the pin is sensed
high, GPIO[1:0] access is disabled; if it is low, GPIO[1:0] access is
enabled. Additionally, if GPIO[1:0] access has been enabled through the
MAD[7] pin and if GPIO0 and/or GPIO1 are sensed low after chip reset,
GPIO[1:0] access is disabled. If GPIO[1:0] access through configuration
space is enabled, the GPIO0 and GPIO1 pins cannot be controlled from
the
General Purpose Pin Control (GPCNTL)
and
registers, but are observable from the
register. When GPIO[1:0] access is enabled, the Serial
Interface Control register at configuration addresses 0x34–0x35 controls
the GPIO0 and GPIO1 pins. For more information on GPIO[1:0] access,
refer to the Serial Interface Control register description in
For more information on the GPIO pins, see
Chapter 4, “Signal Descriptions.”
This does not apply to the LSI53C875E.
Note:
The LSI Logic SDMS software controls the GPIO0 and
GPIO1 pins using the
and
registers.
Therefore, if using SDMS software, do not connect a 4.7 k
Ω
resistor between MAD[7] and Vss.