Avago Technologies LSI8751D User Manual
Page 216
6-20
Instruction Set of the I/O Processor
R
Reserved
[23:20]
ENDID[3:0]
Encoded SCSI Destination ID
[19:16]
This 4-bit field specifies the destination SCSI ID for an I/O
instruction.
R
Reserved
[15:11]
CC
Set/Clear Carry
10
This bit is used in conjunction with a Set or Clear
instruction to set or clear the Carry bit. Setting this bit with
a Set instruction asserts the Carry bit in the ALU. Clear-
ing this bit with a Clear instruction deasserts the Carry bit
in the ALU.
TM
Set/Clear Target Mode
9
This bit is used in conjunction with a Set or Clear
instruction to set or clear Target mode. Setting this bit
with a Set instruction configures the LSI53C875 as a
Target device (this sets bit 0 of the
register). Clearing this bit with a Clear
instruction configures the LSI53C875 as an Initiator
device (this clears bit 0 of the SCNTL0 register).
R
Reserved
[8:7]
ACK
Set/Clear SACK/
6
R
Reserved
[5:4]
ATN
Set/Clear SATN/
3
These two bits are used in conjunction with a Set or Clear
instruction to assert or deassert the corresponding SCSI
control signal. Bit 6 controls the SCSI SACK/ signal. Bit 3
controls the SCSI SATN/ signal.
Setting either of these bits will set or reset the
corresponding bit in the
register, depending on the instruction used. The
Set instruction is used to assert SACK/ and/or SATN/ on
the SCSI bus. The Clear instruction is used to deassert
SACK/ and/or SATN/ on the SCSI bus.
Since SACK/ and SATN/ are Initiator signals, they are not
asserted on the SCSI bus unless the LSI53C875 is
operating as an Initiator or the SCSI Loopback Enable bit
is set in the
register.