Avago Technologies LSI8751D - Manual (Page 191)

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set this bit for access to the SCSI bit-level registers SCSI
Output Data Latch (SODL) , SCSI Bus Control Lines
(SBCL) , and input registers.
Register: 0x4F (0xCF)
SCSI Test Three (STEST3)
Read/Write
TE TolerANT Enable 7
Setting this bit enables the active negation portion of
TolerANT technology. Active negation causes the SCSI
Request, Acknowledge, Data, and Parity signals to be
actively deasserted, instead of relying on external
pull-ups, when the LSI53C875 is driving these signals.
Active deassertion of these signals occurs only when the
LSI53C875 is in an information transfer phase. When
operating in a differential environment or at fast SCSI
timings, TolerANT Active negation should be enabled to
improve setup and deassertion times. Active negation is
disabled after reset or when this bit is cleared. For more
information on TolerANT technology, refer to
Chapter 1,
“General Description.” Set this bit if the ULTRA bit in
SCSI Control Three (SCNTL3) is set.
STR SCSI FIFO Test Read 6
Setting this bit places the SCSI core into a test mode in
which the SCSI FIFO is easily read. Reading the least
significant byte of the
SCSI Output Data Latch (SODL)
register causes the FIFO to unload. The functions are
summarized in the table below.
7 6 5 4 3 2 1 0
TE STR HSC DSI S16 TTM CSF STW
0 0 0 0 0 0 0 0
Register
Name
Register
Operation FIFO Bits
FIFO
Function
SODL Read [15:0] Unload
SODL0 Read [7:0] Unload
SODL1 Read [15:8] None