Avago Technologies LSI8751D User Manual
Page 54
2-30
Functional Description
If the DFE bit is cleared, then the FIFOs must be cleared by setting the
CLF (Clear DMA FIFO) and CSF (Clear SCSI FIFO) bits, or flushed by
setting the FLF (Flush DMA FIFO) bit.
SIEN0 and SIEN1 – The
SCSI Interrupt Enable Zero (SIEN0)
and
registers are the interrupt enable registers
for the SCSI interrupts in
SCSI Interrupt Status Zero (SIST0)
and
DIEN – The
register is the interrupt enable
register for DMA interrupts in
.
DCNTL – When bit 1 in this register is set, the IRQ/ pin is not asserted
when an interrupt condition occurs. The interrupt is not lost or ignored,
but merely masked at the pin. Clearing this bit when an interrupt is
pending immediately causes the IRQ/ pin to assert. As with any register
other than ISTAT, this register cannot be accessed except by a
SCRIPTS instruction during SCRIPTS execution.
2.5.13.3 Fatal vs. Nonfatal Interrupts
A fatal interrupt, as the name implies, always causes SCRIPTS to stop
running. All nonfatal interrupts become fatal when they are enabled by
setting the appropriate interrupt enable bit. Interrupt masking is
discussed
All DMA interrupts (indicated by
the DIP bit in ISTAT and one or more bits in
being
set) are fatal.
Some SCSI interrupts (indicated by the SIP bit in the ISTAT and one or
more bits in
SCSI Interrupt Status Zero (SIST0)
or
being set) are nonfatal.
When the LSI53C875 is operating in Initiator mode, only the Function
Complete (CMP), Selected (SEL), Reselected (RSL), General Purpose
Timer Expired (GEN), and Handshake-to-Handshake Timer Expired
(HTH) interrupts are nonfatal.
When operating in Target mode CMP, SEL, RSL, Target mode: SATN/
active (M/A), GEN, and HTH are nonfatal. Refer to the description for the
Disable Halt on a Parity Error or SATN/ active (Target Mode Only) (DHP)
bit in the
register to configure the chip’s