Maxim Integrated MAXQ7666 - Manual (Page 119)

MAXQ7665/MAXQ7666 User’s Guide
3-29
ADC DUAL-
MODE
(ADCDUL)
ADC CONVERSION
SOURCE
(ADCS2:ADCS0)
ADC CONVERSION
TRIGGER
ADC CONVERSION DESCRIPTION
000 (Timer 0)
001 (Timer 1)
010 (Timer 2)
100 (ADCCNV)
Rising Edge of Conversion Source
• Sets T/H into track mode.
• Track duration is under user control.
• If ADC is in auto shutdown, a minimum of 10 ADC clock cycles power-up delay is
required in addition to 80 cycles PGA settling delay (PGA gain > 1), and 3 cycles
acquisition delay.
• If ADC is not in auto shutdown, a minimum of 40 ADC clock cycles PGA settling
delay (PGA gain > 1) and 3 cycles acquisition delay is required.
Falling Edge of ADCNV
• Sets T/H into hold mode.
• Then SAR conversion executes (13 ADC clock cycles).
101
(Inverted ADCCNV)
Falling Edge of ADCNV
• Sets T/H into track mode.
• Track duration is under user control.
• If ADC is in auto shutdown, a minimum of 10 ADC clock cycles power-up delay is
required in addition to 80 cycles PGA settling delay (PGA gain > 1), and 3 cycles
acquisition delay.
• If ADC is not in auto shutdown, a minimum of 40 ADC clock cycles PGA settling
delay (PGA gain > 1) and 3 cycles acquisition delay is required.
Rising Edge of ADCNV
• Sets T/H into hold mode.
• Then SAR conversion executes (13 ADC clock cycles).
110
(Continuous)
Write 110 to ADCS
Write 110 to ADCS
• Sets T/H into track mode.
• ADC control logic provides the required track duration.
• T/H placed in hold after 43 ADC clock cycles (PGA gain > 1).
• Then SAR conversion executes (13 ADC clock cycles).
Conversion continuously repeated every 56 ADC clock cycles.
1
(Dual-Edge
Mode)
(Note: This mode
is valid only with
PGA gain > 1.)
111
(Start/Busy Bit)
Start/Busy Bit:
Write 1 followed by a
write 0
Write 1 to Start/Busy Bit
• Sets T/H into track mode.
• Track duration is under user control.
• If ADC is in auto shutdown, a minimum of 10 ADC clock cycles power-up delay is
required in addition to 80 cycles PGA settling delay (PGA gain > 1), and 3 cycles
acquisition delay.
• If ADC is not in auto shutdown, a minimum of 40 ADC clock cycles PGA settling
delay (PGA gain > 1) and 3 cycles acquisition delay is required.
Write 0 to Start/Busy Bit
• Sets T/H into hold mode.
• Then SAR conversion executes (13 ADC clock cycles).
Table 3-9. ADC Dual- and Single-Edge Modes
Maxim Integrated