Maxim Integrated MAXQ7666 - Manual (Page 279)

MAXQ7665/MAXQ7666 User’s Guide
9-6
Bit 3: Mode-Fault Flag (MODF). This bit is the mode-fault flag for SPI master mode operation. When mode fault detection is enabled
(MODFE = 1) in master mode, detection of high-to-low transition on the
SS pin signifies a mode fault causes MODF to be set to 1. This
bit must be cleared to 0 by software once set. Setting this bit to logic 1 causes an interrupt if enabled. This flag has no meaning in
slave mode.
0 = No mode fault has been detected.
1 = Mode fault detected while operating as a master (MSTM = 1).
Bit 2: Mode-Fault Enable (MODFE). When to set logic 1, the SS input pin is used for mode fault detection during SPI master mode
operation. When cleared to 0, the SS input has no function. In slave mode, the SS pin always functions as a slave-select input signal
to the SPI module, independent of the setting of the MODFE bit.
Bit 1: Master Mode Enable (MSTM). The MSTM bit functions as the master mode enable bit for the SPI module. Note that this bit can
be set from 0 to 1 only when the
SS signal is deasserted. This bit is automatically cleared to 0 by hardware if a mode fault is detected.
0 = SPI module operates in slave mode when enabled (SPIEN = 1).
1 = SPI module operates in master mode when enabled (SPIEN = 1).
Bit 0: SPI Enable (SPIEN)
0 = SPI module and its baud-rate generator are disabled.
1 = SPI module and its baud-rate generator are enabled.
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