Maxim Integrated MAXQ7666 - Manual (Page 285)

MAXQ7665/MAXQ7666 User’s Guide
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9.3.4 SPI Character Lengths
To flexibly accommodate different SPI transfer data lengths, the character length for any transfer is user configurable through the char-
acter length bit (CHR) in the SPI configuration register. The CHR bit allows selection of either 8-bit or 16-bit transfers.
When loading 8-bit characters into the SPIB data buffer, the byte for transmission should be right justified or placed in the least signif-
icant byte of the word. When a byte transfer completes, the received byte is right justified and can be read from the least significant
byte of the SPIB word. The MSB of the SPIB data buffer is not significant when transmitting and receiving 8-bit characters.
9.4 SPI Transfer Baud Rates
When operating as a slave device, an external master drives the MAXQ7665/MAXQ7666 SPI serial clock. For proper slave operation,
the serial clock provided by the external master should not exceed the system clock frequency divided by 8.
When operating in the master mode, the SPI serial clock is sourced to the external slave device(s). The serial clock baud rate is deter-
mined by the clock-divide ratio (CKR) specified in the SPI clock-divide ratio (SPICK) register. The MAXQ7665/MAXQ7666 SPI module sup-
ports 256 different clock divide ratio selections for serial clock generation. The SCLK clock rate is determined by the following formula:
SPI baud rate = 0.5 x system clock frequency / (CKR7:CKR0 + 1)
Since the SPI baud rate is a function of the system clock frequency, using any of the system clock-divide modes (including power man-
agement mode) alters the baud rate.
Note, however, that once in power management mode (PMME = 1), writes to SPIB in master mode and assertion of the SS pin slave
mode both qualify as switchback sources if enabled (SWB = 1). The MAXQ7665/MAXQ7666 SPI module clocks are halted if the device
is placed into stop mode.
9.5 SPI System Errors
The MAXQ7665/MAXQ7666 SPI module can detect three types of SPI system errors. A mode-fault error arises in a multiple master sys-
tem when more than one SPI device simultaneously tries to be a master. A receive-overrun error occurs when an SPI transfer com-
pletes before the previous character has been read from the receive-holding buffer. The third kind of error, write collision, indicates that
an attempted write to SPIB was detected while a transfer was in progress (STBY = 1).
9.5.1 Mode Fault
When the MAXQ7665/MAXQ7666 SPI device is configured as a master and its mode-fault enable bit (SPICN.2:MODFE) is also set, a
mode-fault error occurs if the
SS input signal is driven low by an external device. This error is typically caused when a second SPI device
attempts to function as a master in the system. In the condition where more than one device is configured as master concurrently, there
is a possibility of bus contention that can cause permanent damage to push-pull CMOS drivers. The mode-fault-error detection is to pro-
vide protection from such damage by disabling the bus drivers. When a mode fault is detected, the following actions are taken imme-
diately.
1) The MSTM bit is forced to logic 0 to reconfigure the SPI device as a slave.
2) The SPIEN bit is forced to logic 0 to disable the SPI module.
3) The mode fault (SPICN.3: MODF) status flag is set. Setting the MODF bit can generate an interrupt if it is enabled.
The application software must correct the system conflict before resuming its normal operation. The MODF flag is set automatically by
hardware, but must be cleared by software once set. Setting the MODF bit to logic 1 by software causes an interrupt if enabled.
Mode-fault detection is optional and can be disabled by clearing the MODFE bit to logic 0. Disabling the mode-fault detection disables
the function of the
SS signal during master mode operation.
Note that the mode-fault mechanism does not provide full protection from bus contention in multiple master, multiple slave systems.
For example, if two devices are configured as master at the same time, the mode-fault-detect circuitry offers protection only when one
of them selects the other as slave by asserting its
SS signal. Also, if a master accidentally activates more than one slave and those
devices try to simultaneously drive their output pins, bus contention can occur without a mode-fault error being generated.
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