Maxim Integrated MAXQ7666 - Manual (Page 156)

MAXQ7665/MAXQ7666 User’s Guide
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C0C.1 = 1, EC96/128 = EC128. In this mode, when EC96/128 = 1 the interrupt flag indicates that either the CAN 0 transmit-error
counter or the CAN 0 receive-error counter has reached an error count of 128, which represents an exceptionally high number
of errors. EC96/128 = 0 indicates that the current transmit-error counter and receive error-counter both have an error count of less
than 128. A change in the state of EC96/128 from either a previous 0 to 1 or from a previous 1 to 0 generates an interrupt if
the ERIE, C0IE, IM4, and IGE* peripheral register bits are set.
Bit 5: CAN 0 Wake-Up Status (WKS). (Read-only). WKS = 0 indicates that CAN 0 is not in a low-power mode. WKS = 1 indicates that
CAN 0 is in a low-power mode, based on the setting of either the SIESTA bit or the power-down mode bit to 1. Clearing both the SIES-
TA bit and power-down enable (PDE) bit forces the WKS bit to 0. A change in the state of WKS from a previous 1 to 0 generates an
interrupt if the STIE, C0IE, IM4, and IGE* peripheral register bits are set.
Bit 4: Receive Status (RXS). The RXS bit functions in two different modes. When the AUTOB bit is set to 1, RXS = 1 indicates that a
message has been successfully received by CAN 0 since the last read of the CAN 0 status register. Note that this does not mean that
the incoming message was or was not stored in a message center, but that the message did not have any errors associated with it
during the reception. Messages that are successfully received but are not stored do not pass the arbitration filtering tests required by
the internal message centers. When the AUTOB bit is cleared to 0, RXS = 1 indicates that a message has been both successfully
received and stored in one of the message centers by CAN 0 since the last read of the CAN 0 status register.
RXS = 0 indicates that no message has been successfully received since the last read of the CAN 0 status register. RXS is only set by the
CAN 0 logic and is not cleared by the CAN controller but is only cleared by the microcontroller software, the CRST bit, or a system reset.
When the RXS bit (0 > 1) provides the interrupt source for an interrupt, the microcontroller is required to read the CAN status register
to clear the internal status-change interrupt flag. (This flag is seen externally by the presence of the 01 state in the CAN interrupt reg-
ister.) Once this flag is cleared, the 01 state in the CAN interrupt register is replaced with either the 00 state for no interrupts pending,
or a lower priority interrupt code related to one of the message centers. If a second successful reception is detected prior to or after
the clearing of the RXS bit in the status register, a second status-change interrupt flag is set to allow a second interrupt to be issued.
Each new successful reception generates an interrupt request independent of the previous state of the RXS bit, as long as the CAN
status register has been read to clear the previous status-change interrupt flag. Note that if the microcontroller sets the RXS bit from a
previous low, it generates an artificial status change interrupt (STIE = 1).
Thus, if RXS is previously set to 0 and a reception was successful, RXS is set to 1 and an interrupt can be asserted if enabled. If the
microcontroller writes a 1 to RXS when RXS was previously 0, RXS is set to 1 and an interrupt can be asserted if enabled. If RXS is pre-
viously set to 1 and a reception was successful, RXS remains set to 1 and an interrupt can be asserted if enabled. If the microcon-
troller writes a 1 to RXS when RXS was previously 1, RXS remains 1 and no interrupt is asserted.
Bit 3: Transmit Status (TXS). TXS = 1 indicates that a message has been successfully transmitted by CAN 0 (error free and acknowl-
edged) since the last read of the CAN 0 status register. TXS = 0 indicates that no message has been successfully transmitted since
the last read of the CAN 0 status register. TXS is only set by the CAN 0 logic and is not cleared by the CAN controller, but is only cleared
by the microcontroller software, the CRST bit, or a system reset.
When the TXS bit (0 > 1) provides the interrupt source for an interrupt, the microcontroller is required to read the CAN status register
to clear the internal status-change interrupt flag. (This flag is seen externally by the presence of the 01 state in the CAN interrupt reg-
ister). Once this flag is cleared, the 01 state in the CAN interrupt register is replaced with either the 00 state for no interrupts pending
or a lower priority interrupt code related to one of the message centers. If a second successful transmission is detected prior to or after
the clearing of the TXS bit in the status register, a second status-change interrupt flag is set to allow a second interrupt to be issued.
Each new successful transmission generates an interrupt request independent of the previous state of the TXS bit, as long as the CAN
status register has been read to clear the previous status-change interrupt flag. Note that if the microcontroller sets the TXS bit from a
previous low, it generates an artificial status change interrupt (STIE = 1).
Thus, if TXS is previously set to 0 and a reception was successful, TXS is set to 1 and an interrupt can be asserted if enabled. If the
microcontroller writes a 1 to TXS when TXS was previously 0, TXS is set to 1 and an interrupt can be asserted if enabled. If TXS is pre-
viously set to 1 and a reception was successful, TXS remains set to 1 and an interrupt can be asserted if enabled. If the microcontroller
writes a 1 to TXS when TXS was previously 1, TXS remains 1 and no interrupt is asserted.
* IM4 enables interrupt requests from Module 4 and is part of the IMR (Module 8, index 6) register. IGE is interrupt global enable and is part of the IC (Module
8, index 5) register.
Maxim Integrated