1 analog power enable register (ape) -7, 2 analog i/o module control and status registers, 1 analog power enable register (ape) – Maxim Integrated MAXQ7666 User Manual
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3.2 Analog I/O Module Control and Status Registers
The analog I/O module uses the following control and status registers.
3.2.1 Analog Power Enable Register (APE)
Register Description:
Analog Power Enable Register
Register Name:
APE
Register Address:
Module 05h, Index 01h
Bits 15, 14, 13, 9, 8, and 2: Reserved. Read 0, write ignored.
Bit 12: I/O Voltage Brownout Detection Enable (VIBE). See
Section 2 for details on this bit.
Bit 11: Digital Voltage Brownout Detection Enable (VDBE). See
Section 2 for details on this bit.
Bit 10: Digital Voltage Reset Enable (VDPE). See
Section 2 for details on this bit.
Bits 7, 6, 5: PGA Gain Setting Bits 2, 1, 0 (PGG2, PGG1, PGG0). These bits set the PGA gain as shown in the following table. The
PGA is bypassed when the PGA gain selected is 1.
Bit 4: Temperature Sensor Enable (TSE). Setting this bit to logic 1 enables the temperature sensor. Clearing this bit to logic 0 turns
off the power to the temperature sensor and disables its operation. The ADCMX4:ADCMX0 bits in the ADC control register determine
if the internal or external temperature sensor configuration is used.
Bit 3: PGA Enable (PGAE). The PGA is enabled when this bit is set to logic 1. Clearing this bit to 0 disables the PGA. The PGAE should
be enabled 5µs before attempting a conversion with a PGA gain other than 1. Note: To bypass the PGA, select a PGA gain of 1
(PGG2:PGG0) and clear the PGAE bit to 0. Setting PGAE = 0 significantly reduces power consumption.
Bit 1: DAC Enable (DACE). Setting this bit to logic 1 enables the DAC block to be ready for conversion. Clearing this bit to logic 0
turns off the power to the DAC block and disables its operation.
Bit 0: ADC Enable (ADCE). Setting this bit to logic 1 enables the ADC block to be ready for conversion. Clearing this bit to logic 0
turns off the power to the ADC block and disables its operation.
MAXQ7665/MAXQ7666 User’s Guide
3-7
Bit #
15 14 13 12 11 10 9
8
Name
— — —
VIBE
VDBE
VDPE
— —
Reset
0 0 0 0 0 1 0 0
Access
r r r rw rw rw r r
Bit #
7 6 5 4 3 2 1 0
Name
PGG2 PGG1 PGG0 TSE PGAE — DACE ADCE
Reset
0 0 0 0 0 0 0 0
Access
rw rw rw rw rw r rw rw
r = read, w = write
Note: This register is cleared to 0400h on all forms of reset.
PGG2:PGG0
PGA GAIN
000
1 (Default)
001
2
010
4
011
8
100
16
101
32
110
Reserved, should not be used
111
Reserved, should not be used
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