Maxim Integrated MAXQ7666 - Manual (Page 206)

MAXQ7665/MAXQ7666 User’s Guide
5-9
• The SPI module’s SS (slave select input) signal is asserted in slave mode.
• A CAN bus activity on its data input (CANRXD) while its interrupt is enabled.
• Active debug mode is entered either by break point match or issuance of the debug command from background mode.
When any of these conditions cause switchback to clear PMME to 0, the system clock rate will then revert back to the divide-by-1 mode
(CD1:CD0 = 00). After PMME is cleared to 0 by switchback, it may not be set back to 1 as long as any of the above conditions are
true.
Bit 2: Power Management Mode Enable (PMME). If the PMME bit is cleared to 0, the values of CD1 and CD0 determine the number
of oscillator (clock source) cycles per system clock cycle. If the PMME bit is set to 1, the values of CD1 and CD0 are ignored and the
system clock operates in a fixed mode of 1 cycle per 256 oscillator cycles (divide by 256). If the PMME bit is set to 1 and switchback
mode has been enabled (SWB = 1), when a switchback source (such as an enabled external interrupt) becomes active, PMME is
cleared to 0 and cannot be set to 1 unless all switchback sources are inactive.
Note: The CD1 and CD0 (CKCN1:CKCN0) bits must both be cleared to 0 before setting the PMME bit to 1.
Bits 1 and 0: Clock Divide Control Bits 1 and 0 (CD1 and CD0). If the PMME bit is cleared, the CD1 and CD0 bits control the num-
ber of oscillator (clock source) cycles required to generate one system clock as follows:
If the PMME bit is set to 1, the values of CD1 and CD0 may not be altered and do not affect the system clock frequency.
PMME CD1 CD0
OSCILLATOR CYCLES PER SYSTEM
CLOCK CYCLE
(CLOCK DIVIDE RATIO)
0 0 0 1
0 0 1 2 (default)
0 1 0 4
0 1 1 8
1 0 0 256
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