5 can 0 receive-error register (c0re) -32, 6 can 0 operation control register (cor) -32 – Maxim Integrated MAXQ7666 User Manual
Page 162
MAXQ7665/MAXQ7666 User’s Guide
4-32
4.2.4.5 CAN 0 Receive-Error Register (C0RE)
Register Description:
CAN 0 Receive-Error Register
Register Name:
C0RE
Register Address:
Module 04h, Index 04h
Bits 15 to 8: Reserved. Read 0, write ignored.
Bits 7 to 0: CAN 0 Receive-Error Register 7 to 0 (C0RE.7 to C0RE.0). This register provides a means of reading the CAN 0 receive-
error counter. New values can be loaded into the receive-error counter through the CAN 0 transmit-error register. C0RE is cleared to
00h following all hardware resets and software resets enabled by the CRST bit in the CAN 0 control register.
4.2.4.6 CAN 0 Operation Control Register (COR)
Register Description:
CAN 0 Operation Control Register
Register Name:
COR
Register Address:
Module 04h, Index 05h
Bits 15 to 8, 2: Reserved. Read 0, write ignored.
Bit 7: CAN 0 Bus Activity Status (CAN0BA). The CAN0BA signal is a latched status bit that is set if a CAN bus activity is detected.
This bit is cleared by a reset or software once set.*
Bit #
15
14
13
12
11
10
9
8
Name
— — — — — — — —
Reset
0 0 0 0 0 0 0 0
Access
r
r
r
r
r
r
r
r
Bit #
7
6
5
4
3
2
1
0
Name CAN0BA
INCDEC
AID
C0BPR7
C0BPR6
—
C0BIE
C0IE
Reset
0 0 0 0 0 0 0 0
Access r
rw
rw
rw
rw
rw
rw
rw
r = read, w = write
Note: This register is cleared to 00h on all forms of reset.
Bit #
15
14
13
12
11
10
9
8
Name
— — — — — — — —
Reset
0 0 0 0 0 0 0 0
Access
r
r
r
r
r
r
r
r
Bit #
7
6
5
4
3
2
1
0
Name
C0RE.7 C0RE.6 C0RE.5 C0RE.4 C0RE.3 C0RE.2 C0RE.1 C0RE.0
Reset
0 0 0 0 0 0 0 0
Access
r
r
r
r
r
r
r
r
r = read
*A
change in the state of CAN0BA from a previous 0 to 1 generates an interrupt if the C0BIE, IM4, and IGE peripheral register bits are set.
Maxim Integrated