Maxim Integrated MAXQ7666 - Manual (Page 218)

5.5.2 Switchback Mode
When power management mode is active, the MAXQ7665/MAXQ7666 operate at a reduced clock rate. Although execution continues
as normal, peripherals that base their timing on the system clock such as the UART module and the SPI module may be unable to
operate normally or at a high enough speed for proper application response. Additionally, interrupt latency is greatly increased.
The switchback feature is used to allow a processor running under power management mode to switch back to normal mode quickly
under certain conditions that require rapid response. Switchback is enabled by setting the SWB bit (CKCN.3) to 1. If switchback is
enabled, the MAXQ7665/MAXQ7666 running power management mode automatically clears the PMME bit to 0 and returns to normal
undivided clock rate when any of the following conditions occur:
• An external interrupt condition occurs on a port pin and the corresponding external interrupt is enabled.
• An active-low transition occurs on the UART serial receive-input line (modes 1, 2, and 3) and data reception is enabled.
• The SBUF0 register is written to send an outgoing byte through the UART and transmission is enabled.
• The SPIB register is written in master mode (STBY = 1) to send an outgoing character through the SPI module and transmis-
sion is enabled.
• The SPI module’s SS (slave select input) signal is asserted in slave mode.
• CAN bus activity on its data input (CANRXD) while its interrupt is enabled.
• Active debug mode is entered either by break point match or issuance of the debug command from background mode.
If any of the above conditions are true (a switchback source is active) and SWB has been set to logic 1, the PMME bit cannot be writ-
ten to enter power management mode. This is to prevent the MAXQ7665/MAXQ7666 from accidentally reducing the clock rate during
the service of an external interrupt or serial port activity.
5.5.3 Stop Mode
Stop mode disables all circuits within the MAXQ7665/MAXQ7666 including the watchdog timer and its clock source (the internal
7.6MHz RC oscillator). All clock sources, timers, and peripherals are halted, and no code execution occurs. The system clock is
stopped, and all processing activity is halted. Once in stop mode, the MAXQ7665/MAXQ7666 are in a mostly static state, with power
consumption determined mainly by leakage currents.
Stop mode is invoked by setting the STOP bit (CKCN.4) to 1. The MAXQ7665/MAXQ7666 enter stop mode immediately once the
instruction that sets the STOP bit is executed. Entering stop mode does not affect the settings of the clock control bits; this allows the
processor to return to its original operating frequency following stop mode removal.
The MAXQ7665/MAXQ7666 exit stop mode if any of the following conditions occur:
• An external reset signal is applied to the RESET pin.
• An external interrupt condition occurs on one of the port pins and the corresponding external interrupt is enabled.
• A CAN bus activity on its data input (CANRXD) while its interrupt is enabled.
• A brownout interrupt condition on DVDD or DVDDIO (if brownout detection and corresponding interrupt is enabled).
• A power-on/brownout reset (if brownout reset detection is enabled (VDPE = 1)).
Note that exiting stop mode via external reset or power-on/brownout reset causes the processor to undergo a normal reset cycle (see
Section 2), as opposed to resuming execution at the point at which it entered stop mode. Exiting stop mode by means of an external
interrupt or CAN bus activity interrupt causes the processor to resume execution at the instruction following the one which set the STOP
bit (and then immediately vector to the interrupt service routine).
When stop mode is exited, the MAXQ7665/MAXQ7666 execution resumes as follows:
• If the internal 7.6MHz RC oscillator is selected as the system clock source (RCE = 1 and XT = 0), execution will resume using
the 7.6MHz RC oscillator as the system clock source following a delay of four 7.6MHz RC oscillator cycles.
• If the high-frequency oscillator is selected as the system clock source (HFE = 1 and XT = 1), execution will resume using the
internal 7.6MHz RC oscillator as the system clock source following a delay of four 7.6MHz RC oscillator cycles. After a warmup
delay of 4096 high-frequency oscillator cycles, the system clock source will switch over to the high-frequency oscillator
automatically.
MAXQ7665/MAXQ7666 User’s Guide
5-21
Maxim Integrated