Maxim Integrated MAXQ7666 - Manual (Page 80)

MAXQ7665/MAXQ7666 User’s Guide
2-8
2.2.2 Analog Power Enable Register (APE)
The APE register contains the power-enable bits to control and turn on/off the DVDDIO and DVDD power-supply voltage monitoring.
Register Description: Analog Power Enable Register
Register Name: APE
Register Address: Module 05, Index 01h
Bits 15, 14, 13, 9, 8, and 2: Reserved. Read 0, write ignored.
Bit 12: I/O Voltage Brownout Detection Enable (VIBE). The DVDDIO brownout detection is enabled when this bit is set to logic 1. An
interrupt request is generated if the DVDDIO brownout interrupt enable (VIOBIE in the AIE register) bit is set and the voltage monitor
detects the DVDDIO voltage falling in the threshold range determined by the VIOBI[1:0] bits in the VMC register.
Note: To be acknowledged by the microcontroller interrupt logic, this interrupt request must also be enabled by the IGE bit in the IC
register and the IM5 mask in the IMR peripheral register.
Bit 11: Digital Voltage Brownout Detection Enable (VDBE). The DVDD brownout detection is enabled when this bit is set to logic 1.
An interrupt request is generated if the DVDD brownout interrupt enable (DVBIE in the AIE register) bit is set and the voltage monitor
detects the DVDD voltage falls in the threshold range determined by the VDBI[1:0] bits in the VMC register.
Note: To be acknowledged by the microcontroller interrupt logic, this interrupt request must also be enabled by the IGE bit in the IC
register and the IM5 mask in the IMR peripheral register.
Bit 10: Digital Voltage Brownout Reset Enable (VDPE). The DVDD brownout reset supervisor is enabled when this bit is set to logic
1. A reset state is generated to halt program execution if the DVDD voltage falls in the threshold range determined by the VDBR[1:0]
bits in the VMC register. This bit defaults to logic 1 on reset. Clearing this bit to 0 disables the brownout reset supervisor.
Bits 7, 6, 5: PGA Gain Setting Bits 2, 1, 0 (PGG2, PGG1, PGG0). See Section 3 for more information on these register bits.
Bit 4: Temperature Sensor Enable (TSE). See Section 3 for more information on this register bit.
Bit 3: Programmable Gain Amp Enable (PGAE). Section 3 for more information on this register bit.
Bit 1: DAC Enable (DACE). See Section 3 for more information on this register bit.
Bit 0: ADC Enable (ADCE). See Section 3 for more information on this register bit.
Bit # 15 14 13 12 11 10 9 8
Name — — — VIBE VDBE VDPE — —
Reset 0 0 0 0 0 1 0 0
Access r r r rw rw rw r r
Bit # 7 6 5 4 3 2 1 0
Name PGG2 PGG1 PGG0 TSE PGAE — DACE ADCE
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw r rw rw
r = read, w = write
Note: This register is cleared to 0400h on all forms of reset.
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