Maxim Integrated MAXQ7666 - Manual (Page 157)

MAXQ7665/MAXQ7666 User’s Guide
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Bits 2, 1, 0: CAN 0 Bus Error Status 2, 1, 0 (ER2, ER1, ER0). The ER2:ER0 bits indicate the first type of error that is encountered
within a CAN 0 bus frame. The following states outline the specific error type. The eighth state (111 binary) is automatically pro-
grammed into ER2:ER0, following a read of the CAN 0 status register to establish if there has been a change in an error condition when
doing a future read of the CAN 0 status register. The status data (ER2:ER0) read by the processor must be analyzed or stored in a sep-
arate SRAM location, since the ER2:ER0 bits are automatically set to the 111 state following a read. The 111 state remains in the reg-
ister until a new frame is either transmitted or received, at which time the ER2:ER0 data is undated in relation to the associated trans-
mit or receive message. The ER2:ER0 bits are read-only. Any attempted write to these bits does not affect the bits or the interrupt rela-
tionship associated with their value.
The interrupt error represented by the ER2:ER0 bus-error bits is updated following each reception or transmission. Since the stored
error from one reception or transmission can be reproduced in the next attempted reception or transmission, a new interrupt is gener-
ated whenever a new error condition is detected. This occurs during a reception or transmission, as long as the previous error condi-
tion was removed by a read of the CAN 0 status register.
Thus, if ER2:ER0 is set to 000 or 111 and an error condition occurs, this error condition is stored in the ER2:ER0 bits. An interrupt
request is made to the microcontroller whenever the ER2:ER0 values change from either a 000 or 111 binary state to any state other
than 000 or 111. If a second error occurs prior to the microcontroller performing a read of the CAN status register, the second error is
not stored and the first error condition continues to reside in the ER2:ER0 bits. Once the CAN status register is read by the microcon-
troller, the error status bits are set to 111. If another error occurs after the microcontroller read of the CAN status register, the ER2:ER0
bits are updated with the new error condition.
If two errors come up at the same time, only the one with the higher priority (as given in the following table) is shown. Priority 1 is the
highest and 6 is the lowest. The format error is higher than the bit 1 error, since the format error is always a bit 1 error, but a bit 1 error
is not necessarily a format error. The error value displayed is selected according to relevance, if the two errors occur at the same time.
This is based on which error is the main error and which one is an accompanying error.
The following are descriptions of the different error types.
Bit Stuff Error: The CAN controller detects more than five consecutive bits of an identical state are received in an incoming message.
Format Error: A received message has the wrong format.
Transmit Not Acknowledged Error: A data frame was sent and the requested node did not acknowledged the message.
Bit 1 Error: The CAN attempted to transmit a message and when a recessive bit was transmitted, the CAN bus was found to have a
dominant bit level. This error is not generated when the bit is a part of the arbitration field (identifier and remote retransmission request).
Bit 0 Error: The CAN attempted to transmit a message and when a dominant bit was transmitted, the CAN bus was found to have a
recessive bit level. This error is not generated when the bit is a part of the arbitration field. The bit 0 error is set each time a recessive
bit is received during the period that the CAN processor is recovering from a BUSOFF recovery period.
CRC Error: The calculated CRC of a received message does not match the CRC embedded in the message.
ER2 ER1 ER0 PRIORITY ERROR CONDITIONS
0 0 0 N/A No Error in Last Frame
0 0 1 2 Bit Stuff Error
0 1 0 5 Format Error
0 1 1 4 Transmit Not Acknowledged Error
1 0 0 6 (lowest) Bit 1 Error
1 0 1 1 (highest) Bit 0 Error
1 1 0 3 CRC Error
1 1 1 N/A No Change Since Last C0S Read
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