Maxim Integrated MAXQ7666 - Manual (Page 130)

MAXQ7665/MAXQ7666 User’s Guide
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3.5.4 DAC Power-Down
The DAC is disabled and fully powered down if the DACE bit in the APE register is cleared. Full power-down reduces analog supply
current (refer to the MAXQ7665/MAXQ7666 data sheet for exact current saving) and is ideal for infrequent data conversion. The DACE
bit is the master control for DAC operation and, unless set, no DAC conversion is possible. From full power-down state (DACE = 0),
the DAC may require up to 1µs to power-up and takes 15µs to settle the final value. This occurs in the worst case when no other ana-
log peripheral is enabled and the bias circuit has, therefore, automatically shut down.
Note: The DACI and DACO registers continue to work even if the DAC is powered down, so user could change the DAC output in
power-down mode and then power-up and settle to the new value.
3.5.5 Using the DAC
The following setup is required for using the MAXQ7665/MAXQ7666 DAC.
1) Set DACE bit in analog power enable (APE) register to enable the DAC.
2) If DAC data register loading is going to be controlled from external DACLOAD pin, make sure pin is configured as input in port
0 direction register (PD0).
3) Set up DACLD (DAC load) control bits in DAC control register (DCNT) from external DACLOAD pin or by software write.
4) Initialize DAC input register for load control from DACLOAD falling or rising edge signal.
5) Initialize both DAC input and output register for load control from DACLOAD square-wave signal.
6) For load control by software write, initializing the DAC input register triggers conversion.
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