Maxim Integrated MAXQ7666 - Manual (Page 28)

1.2.4.4 Interrupt Prioritization by Software
All interrupt sources of the MAXQ7665/MAXQ7666 microcontrollers naturally have the same priority. However, when CPU operation vec-
tors to the programmed Interrupt Vector address, the order in which potential interrupt sources are interrogated is left entirely up to the
user, as this often depends upon the system design and application requirements. The Interrupt Mask system register provides the abil-
ity to knowingly block interrupts from modules considered to be of lesser priority and manually re-enable the interrupt servicing by the
CPU (by setting INS = 0). Using this procedure, a given interrupt service routine can continue executing, only to be interrupted by high-
er priority interrupts. An example demonstrating this software prioritization is provided in
Section 1.3.8: Handling Interrupts.
1.2.4.5 Interrupt Exception Window
An interrupt exception window is a noninterruptable execution cycle. During this cycle, the interrupt handler does not respond to any inter-
rupt requests. All interrupts that would normally be serviced during an interrupt exception window are delayed until the next execution cycle.
Interrupt exception windows are used when two or more instructions must be executed consecutively without any delays in between.
Currently, there is a single condition in the MAXQ7665/MAXQ7666 microcontrollers that causes an interrupt exception window: activa-
tion of the prefix (PFX) register.
When the prefix register is activated by writing a value to it, it retains that value only for the next clock cycle. For the prefix value to be
used properly by the next instruction, the instruction that sets the prefix value and the instruction that uses it must always be execut-
ed back to back. Therefore, writing to the PFX register causes an interrupt exception window on the next cycle. If an interrupt occurs
during an interrupt exception window, an additional latency of one cycle in the interrupt handling will be caused as the interrupt will
not be serviced until the next cycle.
1.2.4.6 MAXQ7665/MAXQ7666 Interrupt Sources
Table 1-6 lists all possible interrupt sources for the MAXQ7665/MAXQ7666, along with their corresponding module interrupt enable bits,
local interrupt enable bits, and interrupt flags.
• Each module interrupt enable bit, when cleared to 0, will block interrupts originating in that module from being acknowledged.
When the module interrupt enable bit is set to 1, interrupts from that module are acknowledged (unless the interrupts have been
disabled globally).
• Each local interrupt enable bit, when cleared to 0, will disable the corresponding interrupt. When the local interrupt enable bit
is set to 1, the interrupt will be triggered whenever the interrupt flag is set to 1 (either by software or hardware).
• All interrupt flag bits cause the corresponding interrupt to trigger when the bit is set to 1. These bits are typically set by hard-
ware and must be cleared by software (generally in the interrupt handler routine).
Note that for an interrupt to fire, the following five conditions must exist:
1) Interrupts must be enabled globally by setting IGE (IC.0) to 1.
2) The module interrupt enable bit for that interrupt source’s module must be set to 1.
3) The local interrupt enable bit for that specific interrupt source must be set to 1.
4) The interrupt flag for that interrupt source must be set to 1. Typically, this is done by hardware when the condition that requires
interrupt service occurs.
5) The Interrupt In Service (INS) bit must be cleared to 0. This bit is set automatically upon vectoring to the interrupt handler
address and cleared automatically upon exit (RETI/POPI), so the only reason to clear this bit manually (inside the interrupt han-
dler routine) is allow nested interrupt handling.
MAXQ7665/MAXQ7666 User’s Guide
1-26
Maxim Integrated