Maxim Integrated MAXQ7666 - Manual (Page 315)

11.3.10.3 Data Memory Write Command
When invoking this command, ICDA should be set to the word address of the location to write to, and ICDD should be set to the data
word to write. The input address must be based on the utility ROM memory map, as shown in Section 1.
11.3.10.4 Program Stack Read Command
When invoking this command, ICDA should be set to the address of the starting stack location (value of SP) to read from, and ICDD
should be set to the number of words. The address given in ICDA is the highest value that will be used, as words are popped off the
stack and returned in descending order. Stack words returned by this command are output LSB first.
11.3.10.5 Read Register Map Command
This command outputs all peripheral registers in the range M0[00h] to M5[0Dh], along with a fixed set of system registers. The follow-
ing formatting rules apply to the returned data.
• System registers are output as 8-bit or 16-bit, least significant byte first.
• All peripheral registers are output as 16-bit, least significant byte first. The top byte of 8-bit registers is returned as 00h.
• Non-implemented peripheral registers in the range M0[00h] to M5[0Dh] are returned as 0000h.
• The value of SBUF0, SPIB, C0S, C0DB, C0RMS, C0TMA, and ASR are not read, and this register is returned as 0000h.
The first byte output by this command is the value 174 (AEh), which represents the number of peripheral registers output. Table 11-3
lists the remaining 412 bytes output by this command.
MAXQ7665/MAXQ7666 User’s Guide
11-19
x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF
0x PO0 00 00 00 00 EIF0 00 00 00 00 00 00 00 00
1x PI0 00 00 00 00 EIE0 00 00 00 00 00 00 00 00
2x PD0 00 00 00 00 EIES0 00 00 00 00 00 00 00 00
3x 00 00 00 00 00 00 00 00 00 00 SCON0 SMD0 PR0
4x MCNT MA MB MC2 MC1 MC0 00 00 SPICN
5x SPICF SPICK FCNTL FDATA MC1R MC0R 00 00 00 00
6x 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
7x 00 00 00 00 00 00 00 00 FADDR 00 00 00 00 00 00
8x T2CNA0 T2H0 T2RH0 T2CH0 T2CNA1 T2H1 T2RH1 T2CH1
9x T2CNB0 T2V0 T2R0 T2C0 T2CNB1 T2V1 T2R1 T2C1
Ax T2CFG0 T2CFG1 00 00 00 00 00 00 00 00 00 00 00 00
Bx ICDT0 ICDT1 00 ICDC 00 ICDF 00 ICDB ICDA ICDD TM
Cx T2CNA2 T2H2 T2RH2 T2CH2 00 00 00 00 00 00 00 00
Dx T2CNB2 T2V2 T2R2 T2C2 00 00 00 00 00 00 00 00
Ex T2CFG2 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Fx 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
10x C0C 00 00 C0IR C0TE C0RE COR C0DP 00 00
11x 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
12x 00 00 C0M1C C0M2C C0M3C C0M4C C0M5C C0M6C C0M7C
13x C0M8C C0M9C C0M10C C0M11C C0M12C C0M13C C0M14C C0M15C
14x VMC APE ACNT DCNT DACI 00 00 DACO 00 00
15x ADCD TSO AIE 00 00 OSCC OTP AP APC PSF IC
16x IMR SC IIR CKCN WDCN 00 A[0] A[1] A[2] A[3] A[4]
17x A[5] A[6] A[7] A[8] A[9] A[10] A[11] A[12]
18x A[13] A[14] A[15] IP SP+1 IV LC[0] LC[1]
19x OFFS DPC GR BP DP[0] DP[1]
Table 11-3. Output from DebugReadMap Command
Maxim Integrated