Lucent Technologies MN10285K User Manual
Page 20
General Description
MN102H Series Features
MN102H75K/F75K/85K/F85K LSI User Manual
Panasonic Semiconductor Development Company
19
Panasonic
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Single-byte basic instruction length
The MN102H series has replaced general registers with eight internal CPU
registers divided functionally into four address registers (A0 - A3) and four
data registers (D0 - D3). The program can address a register pair in four or
less bits, and basic instructions such as register-to-register operations and
load/store operations occupy only one byte.
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High-speed pipeline throughput
The MN102H series executes instructions in a high-speed three-stage
pipeline: fetch, decode, execute. With this architecture, the MN102H series
can execute single-byte instructions in only one machine cycle (50 ns at 40
MHz)
.
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Simple instruction set
The MN102H series uses a streamlined set of 41 instructions, designed spe-
cifically for the programming model for embedded applications. To shrink
code size, instructions have a variable length of one to seven bytes, and the
most frequently used basic instructions are single-byte.
Figure 1-1 Conventional vs. MN102H Series Code Assignments
Figure 1-2 Three-Stage Pipeline
7
6
5
4
3
2
1
0
Register specification
(An/Dn)
Conventional code assignment for general register instructions
New Panasonic code assignments
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register specification
(GRn)
1 machine cycle
Time
Instruction 1
Fetch
Decode
Address
calculation
Fetch
Execute
Decode
Address
calculation
Execute
Instruction 2